Creation of clock and data simulation vectors with periodic jitter

Abstract

Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced at each cycle of a clock or data signal. The calculated periodic jitter for each cycle is used to form a new multi-cycle vector incorporating the jitter. If a particular signal to be simulated additionally needs to travel a particular distance such that it would experience a time delay, that time delay may also be incorporated into the jitter equation as a phase shift. So incorporating the time delay into the jitter equation allows for the easy simulation of circuits receiving the vectors without the need to actually design or “lay out” the circuits that imposing the time delay. This technique is particularly useful in efficient modeling, or optimization of, the clock distribution network and sample circuits used to receive data in a SDRAM integrated circuit.

1. A method implementable in a computer system for generating a multi-cycle signal vector suitable for use as the input to a circuit to be simulated in a simulation program, comprising:
 determining in the computer system a time shift value for each of a plurality of cycles of a signal to be simulated, wherein the time shift values vary periodically between the plurality of cycles; 
 applying in the computer system each determined time shift value to create a time shifted vector for each of the plurality of cycles, wherein each time shifted vector comprises a sequence of voltage values each separated by a time step; and 
 concatenating in the computer system the plurality of time shifted vectors to create the multi-cycle signal vector. 
 
     
     
       2. The method of  claim 1 , wherein the signal is a clock signal. 
     
     
       3. The method of  claim 1 , wherein the signal is a data signal. 
     
     
       4. The method of  claim 3 , wherein at least some of the time shifted vectors comprise transitions between logic states in the data signal. 
     
     
       5. The method of  claim 1 , wherein the time shift values are determined using an equation. 
     
     
       6. The method of  claim 5 , wherein the equation is sinusoidal. 
     
     
       7. The method of  claim 5 , wherein the equation is at least a function of a jitter frequency, and a jitter magnitude. 
     
     
       8. The method of  claim 1 , wherein the time shift values represent jitter or noise. 
     
     
       9. A method implementable in a computer system for generating a multi-cycle signal vector suitable for use as the input to a circuit to be simulated in a simulation program, comprising:
 determining in the computer system a time shift value for each of a plurality of cycles of a signal to be simulated, wherein the time shift values vary periodically between the plurality of cycles, and wherein the time shift values are further phase shifted by a phase shift in each of the cycles; 
 applying in the computer system each determined time shift value to create a time shifted vector for each of the plurality of cycles, wherein each time shifted vector comprises a sequence of voltage values each separated by a time step; and 
 concatenating in the computer system the plurality of time shifted vectors to create the multi-cycle signal vector. 
 
     
     
       10. The method of  claim 9 , wherein the signal is a clock signal. 
     
     
       11. The method of  claim 9 , wherein the signal is a data signal. 
     
     
       12. The method of  claim 11 , wherein at least some of the time shifted vectors comprise transitions between logic states in the data signal. 
     
     
       13. The method of  claim 9 , wherein the time shift values are determined using an equation. 
     
     
       14. The method of  claim 13 , wherein the equation is sinusoidal. 
     
     
       15. The method of  claim 13 , wherein the equation is at least a function of a jitter frequency, a jitter magnitude, and the phase shift. 
     
     
       16. The method of  claim 9 , wherein the time shift values represent jitter or noise. 
     
     
       17. The method of  claim 9 , wherein a magnitude of the phase shift corresponds to a delay experienced by the signal prior to arrival at the circuit. 
     
     
       18. A method for simulating the operation of a circuit in an integrated circuit, comprising:
 generating in a computer system a first multi-cycle input vector representing a signal, wherein each cycle of the input vector includes a jitter which is periodical between the cycles, and wherein the jitter is further phase shifted by a phase shift to account for a time delay that the signal must travel within the integrated circuit, 
 wherein the jitter is calculated for each cycle of the input vector using an equation that is at least a function of a jitter frequency, a jitter magnitude, and the time delay; and 
 simulating the operation of the circuit in the computer system using at least the multi-cycle input vector as an input. 
 
     
     
       19. The method of  claim 18 , wherein the signal is a clock signal. 
     
     
       20. The method of  claim 18 , wherein the signal is a data signal. 
     
     
       21. The method of  claim 18 , wherein the input vector comprises a sequence of voltage values each separated by a time step. 
     
     
       22. A method for simulating the operation of at least one sample circuit for sampling a data signal using a clock signal in an integrated circuit, comprising:
 generating in a computer system a multi-cycle clock input vector representing the clock signal, wherein each cycle of the clock input vector includes a jitter which is periodical between the cycles, wherein each cycle in the multi-cycle clock input vector comprises a sequence of voltage values each separated by a time step; 
 generating in a computer system a multi-cycle data input vector representing the data signal, wherein each cycle of the data input vector includes a jitter which is periodical between the cycles, and wherein each cycle in the multi-cycle data input vector comprises a sequence of voltage values each separated by a time step; and 
 simulating the operation of the sample circuit in the computer system using the multi-cycle clock input vector and the multi-cycle data input vector as inputs. 
 
     
     
       23. The method of  claim 22 , wherein the either or both of the multi-cycle input vectors is further phase shifted to account for a time delay that the signal or signals must travel within the integrated circuit prior to its or their arrival at the sample circuit. 
     
     
       24. The method of  claim 23 , wherein the jitter is calculated for each cycle of either or both of the input vectors using at least one equation, and wherein the at least one equation is at least a function of a jitter frequency, a jitter magnitude, and the time delay. 
     
     
       25. The method of  claim 22 , wherein the integrated circuit comprises a synchronous dynamic random access memory. 
     
     
       26. The method of  claim 22 , wherein the jitter is calculated for each cycle of the input vectors using at least one equation. 
     
     
       27. The method of  claim 26 , wherein the at least one equation is sinusoidal. 
     
     
       28. The method of  claim 26 , wherein the at least one equation is at least a function of a jitter frequency and a jitter magnitude. 
     
     
       29. A method for simulating the operation of at least one circuit in an integrated circuit, comprising:
 generating in a computer system a first multi-cycle input vector representing a first signal, wherein each cycle of the first multi-cycle input vector includes a jitter which is periodical between the cycles, wherein each cycle in the first multi-cycle input vector comprises a sequence of voltage values each separated by a time step; 
 generating in a computer system a second multi-cycle input vector representing a second signal, wherein each cycle of the second multi-cycle input vector includes a jitter which is periodical between the cycles, and wherein each cycle in the second multi-cycle input vector comprises a sequence of voltage values each separated by a time step; and 
 simulating the operation of the circuit in the computer system using the first and second multi-cycle input vectors as inputs. 
 
     
     
       30. The method of  claim 29 , wherein at least one multi-cycle input vector is further phase shifted to account for a time delay that the signal must travel within the integrated circuit prior to its arrival at the circuit. 
     
     
       31. The method of  claim 30 , wherein the jitter is calculated for each cycle of the at least one input vector using at least one equation, and wherein the at least one equation is at least a function of a jitter frequency, a jitter magnitude, and the time delay. 
     
     
       32. The method of  claim 29 , wherein the integrated circuit comprises a synchronous dynamic random access memory. 
     
     
       33. The method of  claim 29 , wherein the jitter is calculated for each cycle of the input vectors using at least one equation. 
     
     
       34. The method of  claim 33 , wherein the at least one equation is sinusoidal. 
     
     
       35. The method of  claim 33 , wherein the at least one equation is at least a function of a jitter frequency and a jitter magnitude.