High performance chip carrier substrate

Abstract

A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs.

1. A method of fanout redistribution of signal pads on a multilayer chip carrier, comprising:
 providing a layer of dielectric material having a plurality of signal pads formed thereon in a pattern of signal pads within the footprint of at least one chip to be carried therein; 
 providing conductive lines connected to a first set of signal pads of said plurality of signal pads near the edge of said chip footprint extending beyond the edge of said chip footprint to allow signals from said first set of signal pads to escape said chip footprint; and 
 moving a second set of signal pads of said plurality of signal pads closer to the edge of said chip footprint by connecting said second set of signal pads to a corresponding set of signal pads closer to the edge of said chip footprint. 
 
     
     
       2. The method as set forth in  claim 1  including the step of providing at least some of said signal pads moved closer to the edge of said chip footprint with connections to signal pads on another layer of dielectric material below said layer of dielectric material. 
     
     
       3. A method of fanout redistribution of signal pads on a multilayer chip carrier, comprising:
 providing a layer of dielectric material having a plurality of signal pads formed on one surface thereof in a pattern of signal pads within the footprint of at least one chip to be carried therein; 
 providing conductive lines on said one surface connected to a first set of signal pads of said plurality of signal pads near the edge of said chip footprint that extend beyond the edge of said chip footprint to allow signals from said first set of signal pads to escape said chip footprint; and 
 moving a second set of signal pads of said plurality of signal pads closer to the edge of said chip footprint by connecting said second set of signal pads to a corresponding set of signal pads closer to the edge of said chip footprint. 
 
     
     
       4. The method as set forth in  claim 3  including the step of providing at least some of said signal pads moved closer to the edge of said chip footprint with connections to signal pads on another layer of dielectric material attached to said layer of dielectric material.