Die-wafer package and method of fabricating same

Abstract

A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second, opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.

1. A method of fabricating a semiconductor device package comprising:
 fabricating a wafer having at least one semiconductor die site, the at least one semiconductor die site having a plurality of bond pads including at least a first set of bond pads and a second set of bond pads; 
 fabricating at least one singulated semiconductor die having a first plurality of bond pads disposed on a first surface thereof, each of the first plurality of bond pads including an under-bump metallization layer, and a second plurality of bond pads disposed on a second, opposing surface thereof, each of the second plurality of bond pads including an under-bump metallization layer; and 
 placing a first plurality of conductive bumps between the first set of bond pads of the at least one semiconductor die site and at least some of the first plurality of bond pads of the at least one singulated semiconductor die. 
 
     
     
       2. The method according to  claim 1 , further comprising placing a second plurality of conductive bumps on the second set of bond pads of the at least one semiconductor die site connecting the second plurality of conductive bumps therewith. 
     
     
       3. The method according to  claim 2 , further comprising placing a third plurality of conductive bumps on the second plurality of bond pads of the at least one singulated semiconductor die connecting the third plurality of conductive bumps therewith. 
     
     
       4. The method according to  claim 3 , further comprising depositing at least one passivation layer over the second, opposing surface of the at least one singulated semiconductor die and at least a portion of the at least one semiconductor die site. 
     
     
       5. The method according to  claim 4 , further comprising exposing a portion of each of the second plurality of conductive bumps and a portion of each of the third plurality of conductive bumps through the at least one passivation layer. 
     
     
       6. The method according to  claim 5 , wherein exposing a portion of each of the second plurality of conductive bumps and a portion of each of the third plurality of conductive bumps through the at least one passivation layer includes subjecting at least a portion of the at least one passivation layer to a planarization process. 
     
     
       7. The method according to  claim 6 , wherein subjecting at least a portion of the at least one passivation layer to a planarization process includes mechanically planarizing the at least a portion of the at least one passivation layer. 
     
     
       8. The method according to  claim 6 , wherein subjecting at least a portion of the at least one passivation layer to a planarization process includes subjecting the at least a portion of the at least one passivation layer to a chemical-mechanical planarization process. 
     
     
       9. The method according to  claim 5 , wherein exposing a portion of each of the second plurality of conductive bumps and a portion of each of the third plurality of conductive bumps through the at least one passivation layer includes etching at least a portion of the at least one passivation layer. 
     
     
       10. The method according to  claim 5 , further comprising singulating the at least one semiconductor die site and the at least one singulated semiconductor die from a remainder of the wafer. 
     
     
       11. A method of fabricating a semiconductor device package comprising:
 disposing a first plurality of conductive bumps coupling a first set of bond pads of at least one semiconductor die site of a wafer, the at least one semiconductor die site of the wafer having a plurality of bond pads including at least the first set of bond pads and a second set of bond pads, with at least some of a first plurality of bond pads of at least one singulated semiconductor die, each of the first plurality of bond pads including an under-bump metallization layer, the at least one singulated semiconductor die having a second plurality of bond pads disposed on a second, opposing surface thereof, each of the second plurality of bond pads including an under-bump metallization layer. 
 
     
     
       12. The method of  claim 11 , further comprising disposing a second plurality of conductive bumps on the second set of bond pads of the at least one semiconductor die site connecting the second plurality of conductive bumps therewith. 
     
     
       13. The method of  claim 12 , further comprising disposing a third plurality of conductive bumps on the second plurality of bond pads of the at least one singulated semiconductor die connecting the third plurality of conductive bumps therewith. 
     
     
       14. The method of  claim 13 , further comprising forming at least one passivation layer over at least a portion of the at least one semiconductor die site. 
     
     
       15. The method of  claim 14 , further comprising exposing a portion of each of the second plurality of conductive bumps and a portion of each of the third plurality of conductive bumps through the at least one passivation layer. 
     
     
       16. The method of  claim 15 , wherein exposing a portion of each of the second plurality of conductive bumps and a portion of each of the third plurality of conductive bumps includes using a planarization process. 
     
     
       17. A method of forming a semiconductor device package comprising:
 forming a wafer having at least one semiconductor die site, the at least one semiconductor die site having a plurality of bond pads including at least a first set of bond pads and a second set of bond pads; 
 forming at least one singulated semiconductor die having a first plurality of bond pads on a first surface thereof, each of the first plurality of bond pads including an under-bump metallization layer, and a second plurality of bond pads disposed on a second, opposing surface thereof, each of the second plurality of bond pads including an under-bump metallization layer; and 
 forming a first plurality of conductive bumps between and electrically coupling the first set of bond pads of the at least one semiconductor die site with at least some of the first plurality of bond pads of the at least one singulated semiconductor die. 
 
     
     
       18. The method of  claim 17 , further comprising:
 attaching a second semiconductor die to the at least one singulated semiconductor die. 
 
     
     
       19. The method of  claim 17 , further comprising:
 attaching a second semiconductor die to another semiconductor die site on the wafer. 
 
     
     
       20. The method of  claim 19 , further comprising:
 attaching a third semiconductor die to one of the at least one singulated semiconductor die and the second semiconductor die.