Direct capacitance-to-digital converter

Abstract

A direct capacitance-to-digital converter is provided, including a plurality of switches, an ADC, a reference voltage circuit and a trigger unit. By using trigger unit to control a plurality of switches, and combining the reference voltages outputted by the reference voltage circuit, the converter can directly sense the external to-be-measured capacitor and related stray capacitor, and directly convert the capacitance of the to-be-measured capacitor into accurate digital signal. The present invention can be integrated with other sensors into a single chip to form an integrated direct capacitance-to-digital converter.

1. A direct capacitance-to-digital converter, for sensing a stray capacitor related to a to-be-measured capacitor, and directly converting an inductive capacitance of said to-be-measured capacitor into a digital signal, a first end of said stray capacitor being connected to a first end of said to-be-measured capacitor, a second end of said stray capacitor being grounded, said direct capacitance-to-digital converter comprising:
 a first integrator, for receiving an input signal at second end of said to-be-measured capacitor, after integration, generating a first-stage integrator output signal; 
 a second-stage integrator, for receiving said first-stage integrator output signal, after integration, generating a second-stage integrator output signal, said second-stage integrator further comprising an integral capacitor and an integral amplifier, one end of said integral capacitor and an inverted input end of said integral amplifier being connected to input signal of said second-stage integrator, a non-inverted input end of said integral amplifier being grounded, the other end of said integral capacitor and an output end of said integral amplifier being connected to said second-stage integrator output signal; 
 a comparator, for receiving said second-stage integrator output signal, after comparing with a standard voltage, generating said digital signal; and 
 a trigger unit, for generating a plurality of control signals to control first end and second end of said to-be-measured capacitor and said first-stage integrator, said control signals comprising a first switch signal, a second switch signal, a third switch signal, a third inverted switch signal, a fourth switch signal and a fifth switch, said third inverted switch signal being the inverted phase of said third switch signal, high level of said first switch signal not overlapping high level of said fifth switch signal; 
 where said trigger unit sequentially generating high level of said first switch signal, said second switch signal and said third switch signal for sensing voltage of said stray capacitor, and said trigger unit sequentially generating high level of said fourth switch signal and said fifth switch signal for sensing voltage of said to-be-measured capacitor. 
 
     
     
       2. The converter as claimed in  claim 1 , wherein said first-stage integrator further comprises:
 a plurality of switches, controlled by said control signals of said trigger unit, said switches comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch and a ninth switch, said first end of said to-be-measured capacitor being connected to said third switch, said fourth switch and said fifth switch, said second end of to-be-measured capacitor being connected to said first switch, said second switch and said sixth switch; 
 a DAC capacitor, having a first end and a second end; 
 an external compensation capacitor, having a first end connected to said ninth switch and a second end connected to said sixth switch, said seventh switch and said second end of said DAC capacitor; 
 an integral amplifier, having an inverted input end, a non-inverted input end and an output end, said non-inverted input end being grounded, said output end having said first-stage integrator output signal; 
 an integral capacitor, having a first end connected to said inverted input end of said integral amplifier and a second end connected to said output end of said integral amplifier; 
 a bias circuit, for generating a bias voltage; and 
 a reference voltage circuit, for generating a first reference voltage, a second reference voltage, a third reference voltage, a high level reference voltage and a low level reference voltage, said third reference voltage being higher than said second reference voltage, said second reference voltage being higher than said first reference voltage, and said high level reference voltage being higher than said low level reference voltage; 
 where said first switch being controlled by said first switch signal and said fourth switch signal to determine whether to connect said second end of said to-be-measured capacitor and said first reference voltage, said second switch being controlled by said second switch signal to determine whether to connect said second end of said to-be-measured capacitor and said second reference voltage, said third switch being controlled by said first switch signal and said fifth switch signal to determine whether to connect said first end of said to-be-measured capacitor and said first reference voltage, said fourth switch being controlled by said second switch signal and said fourth switch signal to determine whether to connect said first end of said to-be-measured capacitor and said second reference voltage, said fifth switch being controlled by said third switch signal to determine whether to connect said first end of said to-be-measured capacitor and said third reference voltage, said sixth switch being controlled by said third switch signal to determine whether to connect said second end of said to-be-measured capacitor and said second end of said DAC capacitor, said seventh switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said second end of said DAC capacitor and said inverted input end of said integral amplifier, said eighth switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said second end of said DAC capacitor to said low level reference voltage and being controlled by said third inverted switch signal and said fourth switch signal to determine whether to connect said second end of said DAC capacitor to said high level reference voltage, and said ninth switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said first end of said external compensation capacitor to said high level reference voltage and being controlled by said third inverted switch signal and said fourth switch signal to determine whether to connect said first end of said external compensation capacitor to said bias voltage. 
 
     
     
       3. A direct capacitance-to-digital converter, for sensing an inverted stray capacitor and a non-inverted stray capacitor related to an inverted to-be-measured capacitor and a non-inverted to-be-measured capacitor, and directly converting an inductive capacitance of said to-be-measured capacitor into a digital signal, a first end of said inverted stray capacitor and a first end of said non-inverted stray capacitor being grounded, a second end of said inverted stray capacitor being connected to a second end of said inverted to-be-measured capacitor, a second end of said non-inverted stray capacitor being connected to a second end of said non-inverted to-be-measured capacitor, said direct capacitance-to-digital converter comprising:
 a first integrator, for receiving an inverted input signal of said inverted to-be-measured capacitor and a non-inverted input signal of said non-inverted to-be-measured capacitor, after integration, generating an inverted first-stage integrator output signal and a non-inverted first-stage integrator output signal; 
 a second-stage integrator, for receiving said inverted first-stage integrator output signal and said non-inverted first-stage integrator output signal, after integration, generating an inverted second-stage integrator output signal and a non-inverted second-stage integrator output signal, said second-stage integrator further comprising an inverted integral capacitor, a non-inverted integral capacitor and an integral amplifier, one end of said inverted integral capacitor and an inverted input end of said integral amplifier being connected to inverted first-stage integrator output signal of said second-stage integrator, the other end of said inverted integral capacitor and an inverted output end of said integral amplifier being connected to said inverted second-stage integrator output signal, one end of said non-inverted integral capacitor and a non-inverted input end of said integral amplifier being connected to said inverted first-stage integrator output signal of said second-stage integrator, the other end of said non-inverted integral capacitor and a non-inverted output end of said integral amplifier being connected to said second-stage integrator output signal; 
 a comparator, for receiving said inverted second-stage integrator output signal and said non-inverted second-stage integral output signal, after comparing with a standard voltage, generating said digital signal; and 
 a trigger unit, for generating a plurality of control signals to control first end and second end of said inverted to-be-measured capacitor, first end and second end of said non-inverted to-be-measured capacitor and said first-stage integrator, said control signals comprising a first switch signal, a second switch signal, a third switch signal, a third inverted switch signal, a fourth switch signal and a fifth switch, said third inverted switch signal being the inverted phase of said third switch signal, high level of said first switch signal not overlapping high level of said fifth switch signal; 
 where said trigger unit sequentially generating high level of said first switch signal, said second switch signal and said third switch signal for sensing voltages of said inverted stray capacitor and said non-inverted stray capacitor, and said trigger unit sequentially generating high level of said fourth switch signal and said fifth switch signal for sensing voltages of said inverted to-be-measured capacitor and said non-inverted to-be-measured capacitor. 
 
     
     
       4. The converter as claimed in  claim 3 , wherein said first-stage integrator further comprises:
 a plurality of switches, controlled by said control signals of said trigger unit, said switches comprising an inverted first switch, an inverted second switch, an inverted third switch, an inverted fourth switch, an inverted fifth switch, an inverted sixth switch, an inverted seventh switch, an inverted eighth switch, an inverted ninth switch, a non-inverted first switch, a non-inverted second switch, a non-inverted third switch, a non-inverted fourth switch, a non-inverted fifth switch, a non-inverted sixth switch, a non-inverted seventh switch, a non-inverted eighth switch and a non-inverted ninth switch, said first end of said inverted to-be-measured capacitor being connected to said inverted third switch, said inverted fourth switch and said inverted fifth switch, said second end of said inverted to-be-measured capacitor being connected to said inverted first switch, said inverted second switch and said inverted sixth switch, said first end of said non-inverted to-be-measured capacitor being connected to said non-inverted third switch, said non-inverted fourth switch and said non-inverted fifth switch, said second end of said non-inverted to-be-measured capacitor being connected to said non-inverted first switch, said non-inverted second switch and said non-inverted sixth switch; 
 an inverted DAC capacitor, having a first end and a second end; 
 a non-inverted DAC capacitor, having a first end and a second end; 
 an inverted external compensation capacitor, having a first end connected to said inverted ninth switch and a second end connected to said inverted sixth switch, said inverted seventh switch and said second end of said inverted DAC capacitor; 
 a non-inverted external compensation capacitor, having a first end connected to said non-inverted ninth switch and a second end connected to said non-inverted sixth switch, said non-inverted seventh switch and said second end of said non-inverted DAC capacitor; 
 an integral amplifier, having an inverted input end, a non-inverted input end, an inverted output end and a non-inverted output end, said inverted output end having said inverted first-stage integrator output signal and said non-inverted output end having said non-inverted first-stage integrator output signal; 
 an inverted integral capacitor, having a first end connected to said inverted input end of said integral amplifier and a second end connected to said inverted output end of said integral amplifier; 
 a non-inverted integral capacitor, having a first end connected to said non-inverted input end of said integral amplifier and a second end connected to said non-inverted output end of said integral amplifier; 
 a bias circuit, for generating a bias voltage; and 
 a reference voltage circuit, for generating a first reference voltage, a second reference voltage, a third reference voltage, a high level reference voltage and a low level reference voltage, said third reference voltage being higher than said second reference voltage, said second reference voltage being higher than said first reference voltage, and said high level reference voltage being higher than said low level reference voltage; 
 where said inverted first switch being controlled by said first switch signal and said fourth switch signal to determine whether to connect said second end of said inverted to-be-measured capacitor and said first reference voltage, said inverted second switch being controlled by said second switch signal to determine whether to connect said second end of said inverted to-be-measured capacitor and said second reference voltage, said inverted third switch being controlled by said first switch signal and said fifth switch signal to determine whether to connect said first end of said inverted to-be-measured capacitor and said first reference voltage, said inverted fourth switch being controlled by said second switch signal and said fourth switch signal to determine whether to connect said first end of said inverted to-be-measured capacitor and said second reference voltage, said inverted fifth switch being controlled by said third switch signal to determine whether to connect said first end of said inverted to-be-measured capacitor and said third reference voltage, said inverted sixth switch being controlled by said third switch signal to determine whether to connect said second end of said inverted to-be-measured capacitor and said second end of said inverted DAC capacitor, said inverted seventh switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said second end of said inverted DAC capacitor and said inverted input end of said integral amplifier, said inverted eighth switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said second end of said inverted DAC capacitor to said low level reference voltage and being controlled by said third inverted switch signal and said fourth switch signal to determine whether to connect said second end of said inverted DAC capacitor to said high level reference voltage, and said inverted ninth switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said first end of said inverted external compensation capacitor to said high level reference voltage and being controlled by said third inverted switch signal and said fourth switch signal to determine whether to connect said first end of said inverted external compensation capacitor to said bias voltage, and 
 said non-inverted first switch being controlled by said first switch signal and said fourth switch signal to determine whether to connect said second end of said non-inverted to-be-measured capacitor and said first reference voltage, said non-inverted second switch being controlled by said second switch signal to determine whether to connect said second end of said non-inverted to-be-measured capacitor and said second reference voltage, said non-inverted third switch being controlled by said first switch signal and said fifth switch signal to determine whether to connect said first end of said non-inverted to-be-measured capacitor and said first reference voltage, said non-inverted fourth switch being controlled by said second switch signal and said fourth switch signal to determine whether to connect said first end of said non-inverted to-be-measured capacitor and said second reference voltage, said non-inverted fifth switch being controlled by said third switch signal to determine whether to connect said first end of said non-inverted to-be-measured capacitor and said third reference voltage, said non-inverted sixth switch being controlled by said third switch signal to determine whether to connect said second end of said non-inverted to-be-measured capacitor and said second end of said non-inverted DAC capacitor, said non-inverted seventh switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said second end of said non-inverted DAC capacitor and said non-inverted input end of said integral amplifier, said non-inverted eighth switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said second end of said non-inverted DAC capacitor to said low level reference voltage and being controlled by said third inverted switch signal and said fourth switch signal to determine whether to connect said second end of said non-inverted DAC capacitor to said high level reference voltage, and said non-inverted ninth switch being controlled by said third switch signal and said fifth switch signal to determine whether to connect said first end of said non-inverted external compensation capacitor to said high level reference voltage and being controlled by said third inverted switch signal and said fourth switch signal to determine whether to connect said first end of said non-inverted external compensation capacitor to said bias voltage.