Closed loop ramp up for pop and click reduction in an amplifier

Abstract

To reduce pop or click during turn-on, a method and apparatus are provided. Initially, a plurality of current sources in the amplifier is actuated. The amplifier is transitioned from an off-state to an on-state in a class B amplifier mode by de-coupling each input node of an output stage of the amplifier from a voltage rail, and the amplifier is transitioned from the on-state in the class B amplifier mode to an on-state in a class AB amplifier mode by actuating at least a portion of an intermediate circuit in the amplifier.

1. An amplifier comprising:
 a plurality of voltage rails; 
 a plurality of current sources, wherein each current source is actuated by a first signal; 
 an input stage that is adapted to receive a plurality of input voltages, wherein the input stage includes at least one of the plurality of current sources; 
 an intermediate circuit having at least one of the plurality of current sources, wherein at least a portion of the intermediate circuit is actuated by a second signal; 
 an output stage that is coupled to the intermediate circuit at a plurality of input nodes; and 
 a clamp that is coupled to the input nodes, wherein the clamp is actuated by a third signal, and wherein the clamp couples each of the input nodes to at least one of the plurality of voltage rails when actuated, and wherein the first signal actuates the plurality of current sources prior to the third signal de-actuating the clamp when the amplifier is activated, and wherein the third signal de-actuates the clamp prior to the second signal actuating at least a portion of the intermediate circuit when the amplifier is activated. 
 
     
     
       2. The amplifier of  claim 1 , wherein the amplifier is a folded cascode amplifier. 
     
     
       3. The amplifier of  claim 1 , wherein the intermediate circuit further comprises a plurality of branches, wherein each branch includes:
 a first transistor that is adapted to be actuated by the second signal; 
 a plurality of diode-connected transistors coupled in series with the first transistor; and 
 at least one of the plurality of current sources coupled in series between the first transistor and the diode-connected transistors. 
 
     
     
       4. The amplifier of  claim 1 , wherein the output stage further comprises:
 an PMOS FET coupled to a first voltage rail of the plurality of voltage rails at its source, wherein the gate of the PMOS FET is coupled to at least one of the input nodes; and 
 an NMOS FET coupled to a second voltage rail of the plurality of voltage rails at its source, wherein the gate of the NMOS FET is coupled to at least one of the input nodes, and wherein the drain of the NMOST FET is coupled to the drain of the PMOS FET at an output node. 
 
     
     
       5. The amplifier of  claim 4 , wherein the clamp couples the gate of the PMOS FET to the first voltage rail when actuated. 
     
     
       6. The amplifier of  claim 4 , wherein the clamp couples the gate of the NMOS FET to the second voltage rail when actuated. 
     
     
       7. The amplifier of  claim 1 , wherein the input stage further comprises:
 a first PMOS FET that is adapted to receive at least one of the input voltages at its gate; 
 a second PMOS FET that is adapted to receive at least one of the input voltages at its gate; and 
 at least one current source of the plurality of voltage sources coupled between a first voltage rail of the plurality of voltage rails and the sources of the first and second PMOS FETs. 
 
     
     
       8. The amplifier of  claim 1 , wherein the clamp further comprises a plurality of FETs, wherein each FET is coupled between at least one of the voltage rails and at least one of the input nodes, and wherein each FET is gated by the third signal. 
     
     
       9. An apparatus comprising:
 a plurality of voltage rails; 
 a folded cascode amplifier coupled to the voltage rails, wherein the amplifier includes a plurality of current sources, an input stage, and an output stage, and wherein the plurality of current sources are adapted to be actuated by a first signal; 
 an intermediate circuit coupled to the output stage, wherein the intermediate circuit includes at least one of the plurality of current sources, wherein at least a portion of the intermediate circuit is actuated by a second signal; and 
 a clamp that is coupled to the output stage, wherein the clamp is actuated by a third signal, and wherein the clamp couples at least a portion of the output stage to at least one of the voltage rails when actuated, and wherein the first signal actuates the plurality of current sources prior to the third signal de-actuating the clamp when the amplifier is activated, and wherein the third signal de-actuates the clamp prior to the second signal actuating at least a portion of the intermediate circuit when the amplifier is activated. 
 
     
     
       10. The apparatus of  claim 9 , wherein the intermediate circuit further comprises a plurality of braches, wherein each branch includes:
 a first transistor that is adapted to be actuated by the second signal; 
 a plurality of diode-connected transistors coupled in series with the first transistor; and 
 at least one of the plurality of current sources coupled in series between the first transistor and the diode-connected transistors. 
 
     
     
       11. The apparatus of  claim 9 , wherein the output stage further comprises:
 an PMOS FET coupled to a first voltage rail of the plurality of voltage rails at its source, wherein the gate of the PMOS FET is coupled to at least one of the input nodes; and 
 an NMOS FET coupled to a second voltage rail of the plurality of voltage rails at its source, wherein the gate of the NMOS FET is coupled to at least one of the input nodes, and wherein the drain of the NMOST FET is coupled to the drain of the PMOS FET at an output node. 
 
     
     
       12. The apparatus of  claim 9 , wherein the input stage further comprises:
 a first PMOS FET that is adapted to receive at least one of the input voltages at its gate; 
 a second PMOS FET that is adapted to receive at least one of the input voltages at its gate; and 
 at least one current source of the plurality of voltage sources coupled between a first voltage rail of the plurality of voltage rails and the sources of the first and second PMOS FETs. 
 
     
     
       13. The apparatus of  claim 9 , wherein the clamp further comprises a plurality of FETs, wherein each FET is coupled between at least one of the voltage rails and the output stage, and wherein each FET is gated by the third signal. 
     
     
       14. A method for activating an amplifier, the method comprising:
 actuating a plurality of current sources in the amplifier; 
 transitioning the amplifier from an off-state to an on-state in a class B amplifier mode by de-coupling each input node of an output stage of the amplifier from a voltage rail; and 
 transitioning the amplifier from the on-state in the class B amplifier mode to an on-state in a class AB amplifier mode by actuating at least a portion of an intermediate circuit in the amplifier. 
 
     
     
       15. The method of  claim 14 , wherein the step of transitioning the amplifier from an off-state to an on-state in a class B amplifier mode by de-coupling each input node of an output stage of the amplifier from a voltage rail further comprises the step of inputting a logic low voltage into at least one FET. 
     
     
       16. The method of  claim 14 , wherein the step of transitioning the amplifier from the on-state in the class B amplifier mode to an on-state in a class AB amplifier mode by actuating at least a portion of an intermediate circuit in the amplifier further comprises actuating a plurality of branches in the intermediate circuit.