Flash memory device and method of forming the device

Abstract

Cell gate patterns including first portions separated from each other with a first distance and second portions separated from each other with a second distance less than the first distance, and spacers are formed both sidewalls of the pair of cell gate patterns. The spacers formed on the sidewalls of the second portions are removed using a mask pattern. Accordingly, it is possible to prevent increase of an aspect ratio of a gap between the second portions with the small distance. Since the spacers formed on the sidewalls of the second portions separated from each other with the small distance are selectively removed, it is possible to minimize the increase of the aspect ratio of the gap between the second portions. Thus, it is possible to solve various problems which are caused due to occurrence of a void.

1. A method comprising:
 forming a plurality of cell gate patterns over a semiconductor substrate including a first cell gate pattern, a second cell gate pattern adjacent to the first cell gate pattern, a third cell gate pattern adjacent to the second cell gate pattern and a fourth cell gate pattern adjacent to the third cell gate pattern, each cell gate pattern having a first portion and a second portion, wherein the first portion of the second cell gate pattern and the third cell gate pattern are separated from each other by a first distance and the second portions of the second cell gate pattern and the third cell gate pattern are separated from each other by a second distance less than the first distance; 
 forming spacers on both sidewalls of the cell gate patterns; 
 forming a mask pattern covering the first portions of the cell gate patterns; 
 removing the spacers formed on sidewalls of the second portions of the cell gate patterns using the mask pattern as an etching mask; and 
 removing the mask pattern. 
 
   
   
     2. The method of  claim 1 , wherein the first portions of the first cell gate pattern and the second cell gate pattern are separated from each other by a third distance and second portions of the first cell gate pattern and the second cell gate pattern are separated from each other by a fourth distance. 
   
   
     3. The method of  claim 2 , wherein the first distance is equal to the third distance. 
   
   
     4. The method of  claim 2 , wherein the third distance is less than the first distance. 
   
   
     5. The method of  claim 2 , further comprising: after removing the mask pattern,
 forming a planarization insulating film over the entire surface of the semiconductor substrate; 
 forming a plurality of first contact holes in the planarization insulating film exposing the semiconductor substrate and between the first portions of the second cell gate pattern and the third cell gate pattern, 
 forming second contact holes in the planarization film exposing the semiconductor substrate and between the second portions of the first cell gate pattern and the second cell gate pattern; and then 
 forming a contact plug in the first and second contact holes. 
 
   
   
     6. The method of  claim 5 , wherein forming the plurality of first contact holes comprises patterning the planarization insulating film.