Semiconductor device and method of fabricating the same

Abstract

A method of fabricating a semiconductor device includes forming a first vertical pillar over a semiconductor substrate. A spacer is formed over a sidewall of the first vertical pillar. A portion of the semiconductor substrate exposed between the first vertical pillars is etched to form a recess that exposes a second vertical pillar extending below from the first vertical pillar. A sacrificial film is formed over the semiconductor substrate including the recess and a sidewall of the first vertical pillar to fill the recess, the second vertical pillar and the first vertical pillar. A supporting layer is deposited over the sacrificial film and the first vertical pillar. The supporting layer is patterned to form a supporting pattern connecting the first vertical pillar with each other. The sacrificial film is removed to expose the second vertical pillar. A surrounding gate is formed over a sidewall of the second vertical pillar.

1. A method of fabricating a semiconductor device, the method comprising:
 forming a first vertical pillar over a semiconductor substrate; 
 forming a spacer over a sidewall of the first vertical pillar; 
 etching a portion of the semiconductor substrate exposed between the first vertical pillars to form a recess that exposes a second vertical pillar extending below from the first vertical pillar; 
 forming a sacrificial film over the semiconductor substrate including the recess and a sidewall of the first vertical pillar to fill the recess, the second vertical pillar and the first vertical pillar; 
 forming a supporting layer over the sacrificial film and the first vertical pillar; 
 patterning the supporting layer to form a supporting pattern connecting the first vertical pillar with each other; 
 removing the sacrificial film to expose the second vertical pillar; and 
 forming a surrounding gate over a sidewall of the second vertical pillar. 
 
   
   
     2. The method of  claim 1 , wherein the process of forming the first vertical pillar comprises:
 forming a mask pattern over the semiconductor substrate to define the first vertical pillar; and 
 etching a portion of the semiconductor substrate using the mask pattern as an etching mask. 
 
   
   
     3. The method of  claim 2 , wherein the mask pattern comprises a silicon nitride film with a thickness in the range of about 500 Å to about 5,000 Å. 
   
   
     4. The method of  claim 2 , wherein a top surface of the mask pattern is circular or polygonal. 
   
   
     5. The method of  claim 1 , wherein the supporting pattern connects at least four of the first vertical pillars. 
   
   
     6. The method of  claim 5 , wherein the supporting pattern respectively connects at least two of the first vertical pillars along a first direction and a second direction crossing each other. 
   
   
     7. The method of  claim 1 , wherein the supporting layer comprises a silicon oxide film or a silicon nitride film with a thickness in the range of about 200 Å to about 2,000 Å. 
   
   
     8. The method of  claim 1 , wherein the process of removing the sacrificial film is performed using a wet etching method. 
   
   
     9. The method of  claim 1 , further comprising forming a gate insulating film between the second vertical pillar and the surrounding gate. 
   
   
     10. The method of  claim 9 , wherein the process of forming the gate insulating film comprises:
 selectively etching a sidewall of the second vertical pillar; and 
 forming an insulating film over a surface of the second vertical pillar. 
 
   
   
     11. The method of  claim 10 , wherein the process of selectively etching the second vertical pillar includes an isotropic etch. 
   
   
     12. The method of  claim 9 , wherein the gate insulating film comprises a silicon oxide film with a thickness in the range of about 1 nm to about 100 nm. 
   
   
     13. The method of  claim 1 , wherein the surrounding gate comprises one film selected from the group consisting of a polysilicon layer, a metal layer and a combination thereof. 
   
   
     14. The method of  claim 13 , wherein the polysilicon layer is an undoped polysilicon layer or a doped polysilicon layer. 
   
   
     15. The method of  claim 13 , wherein the metal layer comprises one film selected from the group consisting of a titanium layer, a titanium nitride film, a titanium nitride film, a tungsten layer, an aluminum layer, a copper layer, a tungsten silicide layer and combinations thereof. 
   
   
     16. A semiconductor device comprising a vertical transistor fabricated by the method of  claim 1 .