Method for forming split gate flash nonvolatile memory devices

Abstract

Disclosed is a method for forming a non-volatile memory device, comprising the steps of: successively depositing a gate oxide and a floating gate material on a semiconductor substrate; depositing and selectively etching a first dielectric on the floating gate material to form a first dielectric pattern; forming a first floating gate oxide on the floating gate material; selectively etching the floating gate material with using the first dielectric pattern as a mask to form a floating gate pattern; forming an insulating layer on the floating gate pattern; etching a portion of the semiconductor substrate between neighboring floating gate patterns to form a trench in the substrate; depositing a control gate oxide on surfaces of the trench; depositing a control gate material to fill the trench and to cover the substrate surface; depositing a second dielectric on the control gate material; selectively etching the second dielectric and the control gate material to form a control gate pattern and a second dielectric layer; selectively removing the control gate pattern to form a source line pattern which extends from the substrate surface exposed in the trench to top surface of the second dielectric layer on the control gate pattern; forming an insulating layer on surface of the source line pattern; and forming source region in portion of the substrate, which is exposed by the source line pattern.

1. A method comprising:
 forming a plurality of floating gate patterns and floating gate oxide patterns spaced apart on a semiconductor substrate; 
 forming a trench in the semiconductor substrate in the space between the floating gate patterns; 
 forming a control gate pattern in the trench by depositing a control gate material in the trench and then performing a first etching process on the control gate material such that after the first etching process the control gate pattern comprises a first control gate pattern portion extending parallel to the sidewalls of the floating gate patterns and a second control gate pattern portion extending perpendicular to the sidewalls of the floating gate patterns and over the floating gate patterns; 
 forming a dielectric layer pattern on the control gate pattern after forming the trench; 
 simultaneously forming a pair of second control gate patterns and a second trench between the second control gate patterns by performing a second etching process on the control gate pattern to expose a portion of the semiconductor substrate in the trench, wherein the dielectric layer pattern is formed before simultaneously forming the pair of second control gate patterns and the second trench; 
 forming a first oxide layer on a respective sidewall of the second control gate patterns provided in the trench; 
 forming a source region in the exposed portion of the semiconductor substrate in the second trench; and then 
 forming a metal layer filling the second trench and on a portion of the uppermost surface of the second control gate patterns. 
 
   
   
     2. The method of  claim 1 , further comprising, after forming the plurality of floating gate patterns and floating gate oxide patterns and before forming the trench:
 forming a second oxide layer on the floating gate patterns by performing an oxidation process on the floating gate patterns; 
 forming spacers composed of the second oxide layer on sidewalls of the floating gate patterns; 
 forming a third oxide layer on the uppermost surface of the floating gate patterns. 
 
   
   
     3. The method of  claim 1 , further comprising, after forming the trench and before forming the control gate pattern:
 forming a fourth oxide layer on the uppermost surface of the trench. 
 
   
   
     4. The method of  claim 1 , wherein the metal layer comprises aluminum. 
   
   
     5. The method of  claim 1 , wherein electrically insulating the source line pattern comprises:
 forming the first oxide layer by performing an oxidation process on the second control gate patterns. 
 
   
   
     6. A method comprising:
 forming a plurality of floating gate patterns spaced apart on a semiconductor substrate; 
 forming a plurality of oxide layer patterns covering the upper, bottom and side walls of the floating gate patterns; 
 forming a trench in the semiconductor substrate in the space between an adjacent pair of the floating gate patterns; 
 forming a control gate pattern by depositing a control gate material in the trench and then performing a first etching process on the control gate material such that after the first etching process the control gate pattern includes a first control gate pattern portion formed in the trench between the adjacent pair of floating gate patterns and a second control gate pattern portion connected to the first control gate pattern and over the floating gate patterns and also over and contacting the oxide layer patterns formed on the upper walls of the adjacent floating gate patterns; 
 forming a pair of second control gate patterns spaced apart by performing a second etching process on the control gate pattern to expose a portion of the semiconductor substrate at the trench; 
 forming a source region in the exposed portion of the semiconductor substrate; and then 
 forming a source electrode in the space between the second control gate patterns, the source electrode including a first source electrode portion extending parallel to the sidewalls of the second control gate patterns and a second source electrode portion extending parallel to and over the upper surface of second control gate patterns. 
 
   
   
     7. A method comprising:
 forming a plurality of floating gate patterns on a semiconductor substrate; 
 forming a plurality of oxide layer patterns covering the floating gate patterns; 
 forming a trench in the semiconductor substrate in a space between an adjacent pair of the floating gate patterns; 
 depositing a control gate material in the trench and over the semiconductor substrate; 
 forming a control gate pattern by performing a first etching process on the control gate material such that after the first etching process the control gate pattern includes a first control gate pattern portion formed in the trench and a second control gate pattern portion connected to the first control gate pattern, wherein the second control gate pattern has an uppermost surface that lies in a plane above the uppermost surface of the oxide layer patterns and the floating gate patterns; 
 forming a pair of second control gate patterns spaced apart by performing a second etching process on the control gate pattern to expose a portion of the semiconductor substrate at the trench; 
 forming a source region in the exposed portion of the semiconductor substrate; and then 
 forming a source electrode in the space between the second control gate patterns.