Successive approximation register analog to digital converter with improved immunity to time varying noise

Abstract

An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (V REF ). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled V REF signal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same V REF noise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

1. A successive approximation register analog to digital converter (SAR ADC), comprising:
 a differential comparator, 
 a pair of binary weighted capacitor arrays, the capacitor arrays having switch controls coupled thereto that configure each capacitor array for a sampling phase and a bit trial phase, 
 wherein, during the bit trial phase:
 the switch control connects select capacitors of each capacitor array to a reference potential, and 
 the differential comparator rejects as a common mode signal time varying noise elements of the reference potential that are obtained during the bit trial phase. 
 
 
   
   
     2. The SAR ADC of  claim 1 , wherein the reference potential is VDD. 
   
   
     3. The SAR ADC of  claim 1 , wherein the reference potential is at a value intermediate between VDD and ground. 
   
   
     4. The SAR ADC of  claim 1 , wherein, during the bit trial phase,
 for a first capacitor array:
 top plates of a plurality of capacitors in a first common span are connected to a first input of the differential comparator by switch control, 
 bottom plates of the capacitors are connected to either the reference potential or ground based on a capacitor currently subject to test and on any decisions made regarding other previously-tested capacitors; and 
 
 for a second capacitor array:
 top plates of a plurality of capacitors in a second common span are connected to a second in put of the differential comparator by switch control, and 
 bottom plates of the capacitors are selectively connected to the reference potential. 
 
 
   
   
     5. The SAR ADC of  claim 4 , wherein, during the sampling phase:
 for the first capacitor array:
 top plates of the capacitors in the first common span are respectively connected to either the reference potential or ground by switch control, 
 bottom plates of the capacitors in the first common span are connected to an input test voltage; and 
 
 for the second capacitor array, top plates and bottom plates of the capacitors in the second common span are connected to ground. 
 
   
   
     6. The SAR ADC of  claim 4 , wherein, during the sampling phase:
 for the first capacitor array, the switch control selectively connects:
 top plates of each of the capacitors to one of a first pair of intermediate nodes, one node of the first pair being connected to ground and a second node of the first pair being connected to a second potential greater than the reference potential, 
 bottom plates of the capacitors in the first common span to an input test voltage; and 
 
 for the second capacitor array, the switch control selectively connects:
 top plates of each of the capacitors to one of a second pair of intermediate nodes, one node of the second pair being connected to ground and a second node of the second pair being connected to the second potential, 
 bottom plates of select capacitors in the second common span to reference potential, bottom plates of other capacitors in the second common span to or ground. 
 
 
   
   
     7. The SAR ADC of  claim 4 , wherein, during the sampling phase, switch control selects capacitors of the second capacitor array to be connected to the reference potential based on a shape of error distribution associated therewith. 
   
   
     8. The SAR ADC of  claim 4 , wherein, during the sampling phase, switch control selects capacitors of the second capacitor array to be connected to the reference potential based on a coarse estimation of an analog input voltage to be converted to digital. 
   
   
     9. A successive approximation register analog to digital converter (SAR ADC), comprising:
 a differential comparator, 
 a pair of binary weighted capacitor arrays, the capacitor arrays having a capacitor for each bit position of a digital code to be output of the SAR ADC and switch controls coupled thereto that configure each capacitor array for a sampling phase and a bit trial phase, wherein 
 in the sampling phase, the switch controls configure a first one of the binary weighted capacitor array to sample a test voltage and a reference voltage, and 
 in the bit trial phase:
 the switch control connects select capacitors of each capacitor array to a reference potential, and 
 the differential comparator rejects as a common mode signal time-varying noise elements of the reference potential that are obtained during the bit trial phase. 
 
 
   
   
     10. The SAR ADC of  claim 9 , wherein the reference potential is VDD. 
   
   
     11. The SAR ADC of  claim 9 , wherein the reference potential is at a value intermediate between VDD and ground. 
   
   
     12. The SAR ADC of  claim 9 , wherein, during the bit trial phase,
 for a first capacitor array:
 top plates of a plurality of capacitors in a first common span are connected to a first input of the differential comparator by switch control, 
 bottom plates of the capacitors are connected to either the reference potential or ground based on a capacitor currently subject to test and on any decisions made regarding other previously-tested capacitors; and 
 
 for a second capacitor array:
 top plates of a plurality of capacitors in a second common span are connected to a second input of the differential comparator by switch control, and 
 bottom plates of the capacitors are selectively connected to the reference potential. 
 
 
   
   
     13. The SAR ADC of  claim 12 , wherein, during the sampling phase:
 for the first capacitor array:
 top plates of the capacitors in the first common span are respectively connected to either the reference potential or ground by switch control, 
 bottom plates of the capacitors in the first common span are connected to an input test voltage; and 
 
 for the second capacitor array, top plates and bottom plates of the capacitors in the second common span are connected to ground. 
 
   
   
     14. The SAR ADC of  claim 12 , wherein, during the sampling phase:
 for the first capacitor array, the switch control selectively connects:
 top plates of each of the capacitors to one of a first pair of intermediate nodes, one node of the first pair being connected to ground and a second node of the first pair being connected to a second potential greater than the reference potential, 
 bottom plates of the capacitors in the first common span to an input test voltage; and 
 
 for the second capacitor array, the switch control selectively connects:
 top plates of each of the capacitors to one of a second pair of intermediate nodes, one node of the second pair being connected to ground and a second node of the second pair being connected to the second potential, 
 bottom plates of select capacitors in the second common span to reference potential, bottom plates of other capacitors in the second common span to or ground. 
 
 
   
   
     15. The SAR ADC of  claim 12 , wherein, during the sampling phase, switch control selects capacitors of the second capacitor array to be connected to the reference potential based on a shape of error distribution associated therewith. 
   
   
     16. The SAR ADC of  claim 12 , wherein, during the sampling phase, switch control selects capacitors of the second capacitor array to be connected to the reference potential based on a coarse estimation of an analog input voltage to be converted to digital. 
   
   
     17. A control method for a successive approximation register analog to digital converter (SAR ADC), comprising:
 sampling a test voltage during a sampling phase of the SAR ADC, 
 sampling a reference voltage during the sampling phase of the SAR ADC, 
 during a bit trial phase of the SAR ADC:
 switchably connecting respective intermediate nodes of the SAR ADC to respective inputs of a differential comparator, 
 switchably connecting a capacitor representing a first bit subject to test to the reference potential, causing a scaled voltage change corresponding to the reference potential to be input to a first input of the differential comparator, and 
 switchably connecting the scaled voltage change corresponding to the reference potential to be input to a second input of the differential comparator, 
 
 wherein temporal variations of the reference potential that occur during the bit trial phase are presented to the differential comparator as a common mode signal. 
 
   
   
     18. A method of controlling an SAR ADC, comprising:
 generating a coarse estimate of the input voltage indicating one of a plurality of voltage bands in which the input voltage is likely to reside, 
 based on the indicated voltage band, retrieving switch data representing a desired error profile for the SAR ADC, 
 during a sampling phase of the SAR ADC:
 selecting elements of a first capacitor array of the SAR ADC to be connected to a reference potential and sampling the reference potential via the selected elements, 
 sampling an the input voltage via a second capacitor array of the SAR ADC; 
 
 during a bit trial phase of the SAR ADC:
 coupling accumulated charge of the first and second capacitor arrays to a differential comparator of the SAR ADC; 
 switching selected capacitors of the second capacitor array in sequence to the reference potential to test the sampled input voltage, and 
 switching selected capacitors of the first capacitor array to the reference potential, 
 
 wherein time varying contributions of the reference potential are rejected by the differential comparator as a common mode signal for at least one bit trial. 
 
   
   
     19. The method of  claim 18 , further comprising:
 storing switch data of two complementary error profiles, and 
 for each iteration of the method of  claim 18 , selecting at random one of the error profiles for the sampling phase of the respective iteration. 
 
   
   
     20. The method of  claim 18 , wherein the selecting comprises selecting an error profile having a local minimum in a band that corresponds to the indicated voltage band.