Semiconductor device having variable parameter selection based on temperature and test method

Abstract

A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

1. A semiconductor device, comprising:
 a first temperature sensing circuit including a first temperature threshold value; and 
 a voltage generator providing an output voltage having a first potential at an output terminal in response to the first temperature sensing circuit having a first temperature indication signal indicating the temperature of the semiconductor device is less than the first temperature threshold value and providing the output voltage having a second potential at the output terminal in response to the first temperature sensing circuit having a first temperature indication signal indicating the temperature of the semiconductor device is greater than the first temperature threshold value. 
 
   
   
     2. The semiconductor device of  claim 1 , wherein:
 the semiconductor device is a semiconductor memory device and the voltage generator is a periphery voltage generator that provides the output voltage as a periphery power supply potential to peripheral circuits in the semiconductor memory device. 
 
   
   
     3. The semiconductor device of  claim 1 , wherein:
 the semiconductor device is a semiconductor memory device and the voltage generator is an array voltage generator that provides the output voltage as an array power supply potential to a memory array in the semiconductor memory device. 
 
   
   
     4. The semiconductor device of  claim 1 , wherein:
 the first temperature sensing circuit includes a first temperature hysteresis value. 
 
   
   
     5. The semiconductor device of  claim 1 , further including:
 a second temperature sensing circuit including a second temperature threshold value greater than the first temperature threshold value; and 
 the voltage generator providing the output voltage having a third potential at the output terminal in response to the second temperature sensing circuit having a second temperature indication signal indicating the temperature of the semiconductor device is greater than the second temperature threshold value. 
 
   
   
     6. The semiconductor device of  claim 1 , wherein:
 the first temperature threshold value is programmable. 
 
   
   
     7. The semiconductor device of  claim 1 , wherein:
 the semiconductor device is a dynamic random access memory device. 
 
   
   
     8. The semiconductor device of  claim 1 , wherein:
 the voltage generator is coupled to receive a reference voltage and provides the output voltage by multiplying the reference voltage by a multiplication factor. 
 
   
   
     9. The semiconductor device of  claim 1 , wherein:
 the voltage generator is coupled to receive an activation signal, the activation signal is at a first logic level when the semiconductor device is in an active mode of operation and at a second logic level when the semiconductor device is in a standby mode of operation. 
 
   
   
     10. The semiconductor device of  claim 1 , wherein:
 the voltage generator includes a variable resistor coupled to receive the first temperature indication signal. 
 
   
   
     11. The semiconductor device of  claim 1 , wherein:
 the first temperature sensing circuit and the voltage generator are coupled to receive a reference voltage. 
 
   
   
     12. The semiconductor device of  claim 3 , further including:
 a bit line reference voltage generator coupled to receive the array power supply potential. 
 
   
   
     13. The semiconductor device of  claim 4 , wherein:
 the first temperature hysteresis value is programmable. 
 
   
   
     14. The semiconductor device of  claim 5 , wherein:
 the third potential is greater than the second potential. 
 
   
   
     15. The semiconductor device of  claim 8 , wherein:
 the multiplication factor is determined in accordance with at least the first temperature indication signal. 
 
   
   
     16. The semiconductor device of  claim 10 , further including:
 a second temperature sensing circuit including a second temperature threshold value greater than the first temperature threshold value and providing a second temperature indication signal; and 
 the variable resistor includes
 a control section coupled to receive the first and second temperature indication signals and providing at least one temperature range signal; and 
 a resistance section coupled to receive the at least one temperature range signal, the resistance section provides a resistance value in response to the at least one temperature range signal. 
 
 
   
   
     17. The semiconductor device of  claim 11 , wherein:
 the voltage generator provides the output voltage by multiplying the reference voltage by a multiplication factor. 
 
   
   
     18. The semiconductor device of  claim 11 , wherein:
 the reference voltage is an essentially temperature independent reference voltage. 
 
   
   
     19. The semiconductor memory device of  claim 11 , wherein:
 a band gap reference circuit coupled to provide the essentially reference voltage. 
 
   
   
     20. The semiconductor device of  claim 18 , wherein:
 the first temperature sensing circuit provides the first temperature indication signal by comparing the reference voltage with a temperature varying voltage.