Via programmable gate array with offset bit lines

Abstract

Some embodiments of the invention provide a via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. At least some of the configurable circuits are via programmable (“VP”) configured circuits. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several bit lines, where at least one the bit line provides a configuration value to at least one configurable circuit. In some embodiments, at least some bit lines traverse along more than one column or row in the circuit arrangement.

1. A via programmable gate array (“VPGA”) comprising:
 a set of configurable circuits arranged in a circuit arrangement, wherein a plurality of the configurable circuits are via programmable (“VP”) configured circuits; and 
 a plurality of offset bit lines for providing configuration values to at least one particular VP configured circuit, 
 wherein said particular VP configured circuit receives configuration data from a particular set of the offset bit lines through vias that are specifically set to connect the particular set of the offset bit lines to particular input terminals of configuration inputs of the particular VP configured circuit so that the particular VP configured circuit receives a particular configuration data set. 
 
   
   
     2. The VPGA of  claim 1 , wherein the configuration values configure the particular VP configured circuit. 
   
   
     3. The VPGA of  claim 2 , wherein a first set of the offset bit lines is on a first layer of the VPGA. 
   
   
     4. The VPGA of  claim 1 , wherein at least one offset bit line provides a configuration value of 0. 
   
   
     5. The VPGA of  claim 1 , wherein at least one offset bit line provides a configuration value of 1. 
   
   
     6. The VPGA of  claim 1 , wherein a set of plurality of the offset bit lines are disjoint bit lines. 
   
   
     7. The VPGA of  claim 1 , wherein the plurality of the offset bit lines traverses along two layers of the IC. 
   
   
     8. The VPGA of  claim 1 , wherein each configurable circuit is a VP configured circuit for configurably performing a set of operations. 
   
   
     9. The VPGA of  claim 1 , wherein the configurable circuits in the circuit arrangement have the same set of circuit elements and the same wiring between the circuit elements. 
   
   
     10. The VPGA of  claim 1 , wherein each configurable circuit is a VP configured interconnect circuit. 
   
   
     11. The VPGA of  claim 1 , wherein each configurable circuit is a VP configured logic circuit. 
   
   
     12. The VPGA of  claim 1 , wherein the circuit arrangement has a plurality of rows and a plurality of columns. 
   
   
     13. A via programmable gate array (“VPGA”) comprising:
 a set of configurable circuits arranged in a circuit arrangement, wherein a plurality of the configurable circuits are via programmable (“VP”) configured circuits; and 
 a plurality of offset bit lines for providing configuration values to at least one particular VP configured circuit, wherein the configuration values configure the particular VP configured circuit 
 wherein a first set of bit lines is on a first layer of the VPGA and a second set of the offset bit lines is on a second layer of the VPGA, wherein the first and second sets of the offset bit lines provide different configuration values. 
 
   
   
     14. A via programmable gate array (“VPGA”) comprising:
 a set of configurable circuits arranged in a circuit arrangement comprising a plurality of rows and a plurality of columns, wherein a plurality of the configurable circuits are via programmable (“VP”) configured circuits; and 
 a plurality of offset bit lines for providing configuration values to at least one particular VP configured circuit, wherein a set of the offset bit lines are long offset bit lines, wherein the long offset bit lines traverse along at least one row and along at least two columns of the circuit arrangement. 
 
   
   
     15. A via programmable gate array (“VPGA”) comprising:
 a set of configurable circuits arranged in a circuit arrangement comprising a plurality of rows and a plurality of columns, wherein a plurality of the configurable circuits are via programmable (“VP”) configured circuits; and 
 a plurality of offset bit lines for providing configuration values to at least one particular VP configured circuit, wherein a set of the offset bit lines are long offset bit lines, wherein the long offset bit lines traverse along at least one column and along at least two rows of the circuit arrangement. 
 
   
   
     16. An electronic device comprising:
 a via programmable gate array (“VPGA”) comprising:
 a set of configurable circuits arranged in a circuit arrangement, wherein a plurality of the configurable circuits are via programmable (“VP”) configured circuits; and 
 a plurality of offset bit lines for providing configuration values to at least one particular VP configured circuit, 
 wherein said particular VP configured circuit receives configuration data from a particular set of the offset bit lines through vias that are specifically set to connect the particular set of the offset bit lines to particular input terminals of configuration inputs of the particular VP configured circuit so that the particular VP configured circuit receives a particular configuration data set.