Imaging device driver, imaging device driving method, and image signal processor

Abstract

An imaging device driver that drives an imaging device, comprising a controller, is provided. The imaging device has the light receiving surface divided into a plurality of pixel blocks. Each pixel block has a plurality of pixels. The pixel generates a pixel signal according to received light amount. The imaging device generates an image signal. The image signal is formed by a plurality of the pixel signals. The image signal corresponds to an optical image of an object during a single frame period. The controller causes the pixel located at a first and a second area in the pixel block to generate the pixel signal in a first and a second frame period, respectively, if the imaging device is driven to output the image signal while thinning out the pixel signals. The second frame period follows the first frame period.

1. An image signal processor for processing an image signal generated by an imaging device, the image signal comprising a plurality of pixel signals and the imaging device including a light receiving surface that is divided into a plurality of pixel blocks with each pixel block being divided into a first area, a second area, a third area, and a fourth area with each area being one of an upper left quadrant, an upper right quadrant, a lower right quadrant, and a lower left quadrant of each pixel block and including at least one pixel that generates one of the pixel signals according to a received light amount, the image signal processor comprising:
 a signal receiver that receives the pixel signal generated by each pixel of the first area of each pixel block during a first frame period, receives the pixel signal generated by each pixel of the second area of each pixel block during a second frame period consecutive to the first frame period, receives the pixel signal generated by each pixel of the third area of each pixel block during a third frame period consecutive to the second frame period, and receives the pixel signal generated by each pixel of the fourth area of each pixel block during a fourth frame period consecutive to the third frame period; and 
 a signal adder that adds corresponding signal components of the pixel signals received by the signal receiver and generated by the pixels of the first, second, third, and fourth areas during the first, second, third, and fourth frame periods respectively. 
 
   
   
     2. The image signal processor according to  claim 1 , wherein the signal adder adds corresponding signal components of the pixel signals most recently generated by the pixels located at the first, second, third, and fourth areas. 
   
   
     3. The image signal processor according to  claim 1 , wherein
 each pixel of the first, second, third, and fourth areas of each pixel block is a pixel array that comprises a first pixel, a second pixel, and a third pixel, the first pixel being covered with a first color filter element, the second pixel being covered with a second color filter element, and the third pixel being covered with a third color filter element, 
 the signal adder adds corresponding signal components of pixel signals generated by the first pixel located at the first, second, third and fourth areas of each pixel block during the first, second, third, and fourth frame periods, respectively, 
 the signal adder adds corresponding signal components of pixel signals generated by the second pixel located at the first, second, third, and fourth areas of each pixel block during the first, second, third, and fourth frame periods, respectively, and 
 the signal adder adds corresponding signal components of pixel signals generated by the third pixel located at the first, second, third and fourth areas of each pixel block during the first, second, third, and fourth frame periods, respectively. 
 
   
   
     4. The image signal processor according to  claim 1 , wherein
 the first area is the upper left quadrant of each pixel block, 
 the second area is the upper right quadrant of each pixel block, 
 the third area is the lower right quadrant of each pixel block, and 
 the fourth area is the lower left quadrant of each pixel block. 
 
   
   
     5. The image signal processor according to  claim 1 , wherein
 the signal receiver receives the pixel signals generated by the first, second, third, and fourth areas during the first, second, third, and fourth frame periods, respectively, when the imaging device is in a first mode for thinning out the pixel signals, and 
 wherein the signal receiver receives the pixel signals generated by the first, second, third, and fourth areas during a single frame period when the imaging device is in a second mode. 
 
   
   
     6. The image signal processor according to  claim 1 , wherein the signal receiver receives the pixel signal generated by each pixel of more than one and less than all of the first, second, third, and fourth areas during each of the first, second, third, and fourth frame periods. 
   
   
     7. An image signal processor for processing an image signal generated by an imaging device, the image signal comprising a plurality of pixel signals and the imaging device including a light receiving surface that is divided into a plurality of pixel blocks with each pixel block being divided into a first area, a second area, a third area, and a fourth area with each area being one of an upper left quadrant, an upper right quadrant, a lower right quadrant, and a lower left quadrant of each pixel block and including at least one pixel that generates one of the pixel signals according to a received light amount, the image signal processor comprising:
 a signal receiver that receives the pixel signal generated by each pixel of the first area of each pixel block during a first frame period, receives the pixel signal generated by each pixel of the second area of each pixel block during a second frame period consecutive to the first frame period, receives the pixel signal generated by each pixel of the third area of each pixel block during a third frame period consecutive to the second frame period, and receives the pixel signal generated by each pixel of the fourth area of each pixel block during a fourth frame period consecutive to the third frame period ;and 
 a signal adder that adds the pixel signals received by the signal receiver and generated by the pixels of the first, second, third, and fourth areas during the first, second, third, and fourth frame periods, respectively, 
 wherein the pixel signals received by the signal receiver from the imaging device are output by the imaging device without averaging of the pixel signals in each frame period. 
 
   
   
     8. The image signal processor according to  claim 7 , wherein the signal adder adds the pixel signals most recently generated by the pixels located at the first, second, third, and fourth areas. 
   
   
     9. The image signal processor according to  claim 7 , wherein
 each pixel of the first, second, third, and fourth areas of each pixel block is a pixel array that comprises a first pixel, a second pixel, and a third pixel, the first pixel being covered with a first color filter element, the second pixel being covered with a second color filter element, and the third pixel being covered with a third color filter element, 
 the signal adder adds pixel signals generated by the first pixel located at the first, second, third and fourth areas of each pixel block during the first, second, third, and fourth frame periods, respectively, 
 the signal adder adds pixel signals generated by the second pixel located at the first, second, third and fourth areas of each pixel block during the first, second, third, and fourth frame periods, respectively, and 
 the signal adder adds pixel signals generated by the third pixel located at the first, second, third and fourth areas of each pixel block during the first, second, third, and fourth frame periods, respectively. 
 
   
   
     10. The image signal processor according to  claim 7 , wherein
 the first area is the upper left quadrant of each pixel block, 
 the second area is the upper right quadrant of each pixel block, 
 the third area is the lower right quadrant of each pixel block, and 
 the fourth area is the lower left quadrant of each pixel block. 
 
   
   
     11. The image signal processor according to  claim 7 , wherein
 the signal receiver receives the pixel signals generated by the first, second, third, and fourth areas during the first, second, third, and fourth frame periods, respectively, when the imaging device is in a first mode for thinning out the pixel signals, and 
 wherein the signal receiver receives the pixel signals generated by the first, second, third, and fourth areas during a single frame period when the imaging device is in a second mode. 
 
   
   
     12. The image signal processor according to  claim 7 , wherein the signal receiver receives the pixel signal generated by each pixel of more than one and less than all of the first, second, third, and fourth areas during each of the first, second, third, and fourth frame periods. 
   
   
     13. An image signal processor for processing an image signal generated by an imaging device, the image signal comprising a plurality of pixel signals and the imaging device including a light receiving surface that is divided into a plurality of pixel blocks with each pixel block being divided into a first area, a second area, a third area, and a fourth area with each area being one of an upper left quadrant, an upper right quadrant, a lower right quadrant, and a lower left quadrant of each pixel block and including at least one pixel that generates one of the pixel signals according to a received light amount, the image signal processor comprising:
 a signal receiver that receives the pixel signal generated by each pixel of more than one and less than all of the first, second, third, and fourth areas of each pixel block during a first frame period, and receives the pixel signal generated by each pixel of the other of the first, second, third, and fourth areas of each pixel block during at least one of a second frame period consecutive to the first frame period and a third frame period consecutive to the second frame period; and 
 a signal adder that adds corresponding signal components of the pixel signals received by the signal receiver and generated by the pixels of the first, second, third, and fourth areas during the first and second frame periods. 
 
   
   
     14. The image signal processor according to  claim 13 , wherein
 the first area is the upper left quadrant of each pixel block, 
 the second area is the upper right quadrant of each pixel block, 
 the third area is the lower right quadrant of each pixel block, and 
 the fourth area is the lower left quadrant of each pixel block. 
 
   
   
     15. The image signal processor according to  claim 13 , wherein
 the signal receiver receives the pixel signals generated by the first, second, third, and fourth areas during the first and second frame periods when the imaging device is in a first mode for thinning out the pixel signals, and 
 wherein the signal receiver receives the pixel signals generated by the first, second, third, and fourth areas during a single frame period when the imaging device is in a second mode.