Dynamic frequency divider

Abstract

A dynamic frequency divider is proposed in which a double mixer is used for the dynamic frequency division. In one example the division is by N, where N≧2 and a positive integer. The dynamic frequency divider further includes an input stage with level shift means, a filter filtering the output signal and providing a feedback signal to the double mixer. In one case, using just one double mixer significantly reduces the power consumption of a dynamic frequency divider and utilizes considerably less space, making it simpler, cheaper and smaller.

1. An integrated circuit comprising:
 a level shift having first and second inputs and first and second outputs, wherein the first input of the level shift is coupled to an input signal; 
 a double mixer having first, second and third inputs and an output, wherein the first input of the double mixer is coupled to the first output of the level shift and wherein the second input of the double mixer is coupled to the second output of the level shift; 
 a filter having first and second inputs and first and second outputs, wherein the output of the double mixer is coupled to the first input of the filter, and wherein the first output of the filter is looped back to the third input of the double mixer; and 
 a buffer having an input and an output, the buffer operable to buffer and output at least an output signal, wherein the input of the buffer is coupled to the second output of the filter, wherein the filter is tunable to a predetermined frequency range by an adjustable reference voltage coupled to the buffer. 
 
   
   
     2. The integrated circuit of  claim 1 , wherein the level shift comprises a plurality of cascaded emitter followers. 
   
   
     3. The integrated circuit of  claim 1 , wherein the level shift comprises a plurality of diodes configured such the input signal is shifted down to a first shift signal and a second shift signal, respectively driving the first and second inputs of the double mixer. 
   
   
     4. The integrated circuit of  claim 1 , wherein the filter comprises a plurality of cascaded emitter followers. 
   
   
     5. The integrated circuit of  claim 1 , configured as a dynamic frequency divider that divides by N, where N≧2 and a positive integer. 
   
   
     6. A communication device comprising at least one radio-frequency integrated circuit, characterized by a dynamic frequency divider of  claim 5 . 
   
   
     7. A dynamic frequency divider by N, where N≧2 and a positive integer, comprising:
 a first divider input operable to receive a first input signal; 
 level shift means comprising a first level-shift input and a plurality of level-shift outputs, wherein said first level-shift input is coupled to said first divider input; 
 a double mixer comprising first and second double-mixer input and a first double-mixer output, wherein said first double-mixer input is coupled to a first level-shift output and wherein said second double-mixer input is coupled to said second level-shift output; 
 filter means comprising a first filter-input and a plurality of filter outputs, wherein said first double-mixer output is coupled to said first filter input, and wherein a first filter output is looped back to a third double-mixer input; 
 buffer means comprising a first buffer input and a first buffer output, operable to buffer and output at least a first output signal, wherein said first buffer input is coupled to a second filter output, wherein the filter means is tunable to a predetermined frequency range by an adjustable reference voltage of the buffer. 
 
   
   
     8. The dynamic frequency divider of  claim 7 , wherein the level shift means comprise a plurality of cascaded emitter followers. 
   
   
     9. The dynamic frequency divider of  claim 7 , wherein the level shift means comprise a plurality of diodes that are arranged such that the first input signal is shifted down to a first shift signal and a second shift signal, respectively driving said first and second double-mixer input. 
   
   
     10. The dynamic frequency divider of  claim 7 , wherein the filter means comprise a plurality of cascaded emitter followers. 
   
   
     11. The dynamic frequency divider of  claim 7  further comprising a second divider input operable to receive a second input signal. 
   
   
     12. A method of dynamic frequency division comprising:
 level shifting a first input signal down to a first shift signal and a second shift signal; 
 driving a first input of a double mixer with the first shift signal and driving a second input of the double mixer with the second shift signal; 
 applying an output signal from the double mixer to a filter and looping a first output of the filter back to a third input of the double mixer; 
 applying a second output of the filter to a buffer and providing an output signal at an output of the buffer; and 
 tuning the filter to a predetermined frequency range by an adjustable reference voltage coupled to the buffer. 
 
   
   
     13. The method of  claim 12 , further comprising dividing the first input signal by 2. 
   
   
     14. The method of  claim 12 , further comprising dividing the first input signal by N, where N≧2 and a positive integer. 
   
   
     15. The method of  claim 12 , wherein the level shift comprises a plurality of cascaded emitter followers. 
   
   
     16. The method of  claim 12 , wherein the filter comprises a plurality of cascaded emitter followers. 
   
   
     17. The method of  claim 12 , further comprising level shifting a second input signal.