Increase productivity at wafer test using probe retest data analysis

Abstract

Disclosed is a method and system for wafer/probe testing of integrated circuit devices after manufacture. The invention begins by testing an initial group of devices (e.g., integrated circuit chips) to produce an initial failing group of devices that failed the testing. The devices in the initial failing group are identified by type of failure. Then, the invention retests the devices in the initial failing group to identify a retested passing group of devices that passed the retesting. Next, the invention analyzes the devices in the retested passing group which allows the invention to produce statistics regarding the likelihood that a failing device that failed the initial testing will pass the retesting according to the type of failure. Then, the invention evaluates these statistics to determine which types of failures have retest passing rates above a predetermined threshold. From this, the invention produces a database comprising an optimized retest table listing the types of defects that are approved for retesting.

1. A system for testing integrated circuit devices after manufacture, said system comprising:
 a tester testing and retesting devices; 
 a database comprising a listing of types of defects approved for retesting, wherein said types of defects approved for retesting are based upon previously acquired statistics that indicate which types of defects have retest passing rates, after initially failing testing, above a predetermined threshold; and 
 a processor in communication with said tester and said database, wherein said processor performs the following:
 directs said tester to test a group of devices to produce a failing group of devices that failed said testing, said devices in said failing group being identified by type of defect; 
 sorts said failing group into devices that have at least one of said types of defects approved for retesting and into devices that do not have said types of defects approved for retesting; and 
 
 directs said tester to retest only said devices in said failing group that have at least one of said types of defects approved for retesting. 
 
     
     
       2. The system in  claim 1 , wherein said database includes types of defects associated with testing errors within said types of defects approved for retesting. 
     
     
       3. The system in  claim 1 , wherein said tester comprise a probe-type tester. 
     
     
       4. The system in  claim 1 , wherein said processor optimizes said retesting of said devices when controlling said tester. 
     
     
       5. The system in  claim 1 , wherein said database comprises an optimized retest table. 
     
     
       6. The system in  claim 1 , wherein said statistics of said types of defects relate to the same type of device being tested. 
     
     
       7. A system for testing integrated circuit devices after manufacture, said system comprising:
 a tester testing an initial group of devices to produce an initial failing group of devices that failed said testing of said initial group, said devices in said initial failing group being identified by type of defect and retesting all of said devices in said initial failing group to identify a retested passing group of devices that passed said retesting; and, 
 a processor in communication with said tester, said processor analyzing said devices in said retested passing group to produce statistics regarding the likelihood that a failing device will pass said retesting according to said type of defect and evaluating said statistics to determine which types of defects have retest passing rates above a predetermined threshold to produce a listing of types of defects approved for retesting, 
 said tester further testing an additional group of devices different from said initial group to produce an additional failing group of devices that failed said testing of said additional group, said devices in said additional failing group being identified by type of defect, 
 said processor further sorting said additional failing group, based on said listing, into devices that have types of defect approved for retest and into devices that do not have said types of defects approved for retesting, and 
 said tester further retesting only said devices in said additional failing group that have at least one of said types of defects approved for retesting. 
 
     
     
       8. The system in  claim 7 , wherein said tester comprise a probe-type tester. 
     
     
       9. The system in  claim 7 , further comprising a database adapted to store said listing and wherein said listing comprises an optimized retest table. 
     
     
       10. The system in  claim 7 , wherein said initial group of devices and said additional groups of devices comprise the same type of device. 
     
     
       11. A system for testing integrated circuit devices after manufacture, said system comprising:
 a tester testing and retesting devices; 
 a database comprising a listing of types of defects approved for retesting, wherein said types of defects approved for retesting are based upon previously acquired statistics that indicate which types of defects have retest passing rates, after initially failing testing, above a predetermined threshold; and 
 a processor in communication with said tester and said database, wherein said processor performs the following:
 directs said tester to test a group of devices to produce a failing group of devices that failed said testing, said devices in said failing group being identified by type of defect; 
 sorts said failing group into devices that have at least one of said types of defects approved for retesting and into devices that do not have said types of defects approved for retesting; and 
 
 directs said tester to retest only said devices in said failing group that have at least one of said types of defects approved for retesting, 
 wherein said database comprises an optimized retest table. 
 
     
     
       12. The system in  claim 11 , wherein said database includes types of defects associated with testing errors within said types of defects approved for retesting. 
     
     
       13. The system in  claim 11 , wherein said tester comprise a probe-type tester. 
     
     
       14. The system in  claim 11 , wherein said processor optimizes said retesting of said devices when controlling said tester. 
     
     
       15. The system in  claim 11 , wherein said statistics of said types of defects relate to the same type of device being tested.