US7566930B2ExpiredUtilityA1

Nonvolatile memory device and method for fabricating the same

Assignee: DONGBU ELECTRONICS CO LTDPriority: Dec 29, 2005Filed: Dec 27, 2006Granted: Jul 28, 2009
Est. expiryDec 29, 2025(expired)· nominal 20-yr term from priority
Inventors:Heong Jin Kim
H10W 20/056H10D 64/035H10D 30/6894H10D 30/0411H10D 30/683
47
PatentIndex Score
0
Cited by
8
References
8
Claims

Abstract

A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the inner wall of the trench and the first electrode layer; a junction area formed on the active area; a second gate oxide layer formed on the entire surface of the substrate including the first electrode layer, the first gate oxide layer, the trench and the junction area; a tunnel oxide layer formed on a part of the second gate oxide layer corresponding to the active area; and a second electrode layer formed on the active area and in the trench.

Claims

exact text as granted — not AI-modified
1. A nonvolatile memory device, comprising:
 a substrate having a plurality of isolation areas and active areas; 
 a first trench in at least one of the isolation areas; 
 a first gate oxide layer in the first trench; 
 a control gate on the first gate oxide layer; 
 a junction area in at least one of the active areas; 
 a second gate oxide on a surface of the substrate including the control gate, the first gate oxide layer, and the junction area; 
 a tunnel oxide in a part of the second gate oxide layer in the active areas; and 
 a floating gate formed over the control gate, second oxide layer and tunnel oxide. 
 
   
   
     2. The nonvolatile memory device of  claim 1 , wherein the first gate oxide layer has uniform thickness in the trench. 
   
   
     3. The nonvolatile memory device of  claim 1 , wherein the control gate is in contact with the first gate oxide layer and the second gate oxide layer. 
   
   
     4. The nonvolatile memory device of  claim 1 , wherein the control gate is formed across an entire bottom surface and along entire side surfaces of the first trench on the first gate oxide layer. 
   
   
     5. The nonvolatile memory device of  claim 1 , wherein the tunnel oxide has a thickness less than that of the second gate oxide layer in the active area. 
   
   
     6. The nonvolatile memory device of  claim 1 , wherein the junction area comprises a source on a first side of the first trench and a drain on an opposite side of the first trench. 
   
   
     7. The nonvolatile memory device of  claim 1 , further comprising an access gate in a part of one of the active areas not occupied by the floating gate. 
   
   
     8. The nonvolatile memory device of  claim 7 , wherein the access gate comprises a same material and has a same thickness as the floating gate in the one active area outside the first trench.

Join the waitlist — get patent alerts

Track US7566930B2 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.