Method for manufacturing a semiconductor device including interconnections having a smaller width

Abstract

A method for manufacturing a semiconductor device includes the steps of forming an interconnection layer including a top tungsten layer, forming a mask pattern on the tungsten layer, nitriding a portion of the tungsten layer in a plasma nitriding process to form a tungsten nitride layer, etching the tungsten nitride layer while leaving the mask pattern on the tungsten layer, and patterning the interconnection layer by using the mask pattern as an etching mask.

1. A method for manufacturing a semiconductor device comprising consecutively:
 forming an interconnection layer overlying a substrate, said interconnection layer including a tungsten layer as a top layer thereof; 
 forming a mask pattern on said tungsten layer; 
 forming a tungsten nitride layer on a portion of said tungsten layer exposed from said mask pattern; 
 etching said tungsten nitride layer while leaving said mask pattern on said tungsten layer; and 
 patterning said interconnection layer by using said mask pattern as an etching mask to thereby form interconnections. 
 
   
   
     2. The method according to  claim 1 , wherein said etching reduces a pattern width of said mask pattern. 
   
   
     3. The method according to  claim 1 , wherein said etching etches said tungsten nitride layer in an isotropic etching condition providing a power etch rate for said tungsten nitride layer than for said hard mask. 
   
   
     4. The method according to  claim 3 , wherein said mask pattern includes silicon nitride. 
   
   
     5. The method according to  claim 1 , wherein said interconnection layer includes a barrier layer underlying said tungsten layer. 
   
   
     6. The method according to  claim 1 , wherein said tungsten nitride layer forming includes nitriding said tungsten layer in a plasma nitriding process. 
   
   
     7. The method according to  claim 1 , wherein said tungsten nitride layer forming, said tungsten nitride layer etching and said interconnection layer patterning are conducted in a common chamber.