Ground biased bitline register file

Abstract

In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry is used to bias a read bitline when the memory cell is not performing a read operation.

1. An apparatus comprising
 a memory cell; 
 ground biased write control circuitry to bias write and writebar bitlines to ground when the memory cell is not performing a write operation; 
 ground biased read control circuitry to bias a read bitline to ground when the memory cell is not performing a read operation; and 
 a write bitline keeper to maintain one of the write and writebar bitlines at a predetermined voltage during consecutive write cycles. 
 
   
   
     2. The apparatus of  claim 1 , wherein the ground biased write control circuitry includes a first transistor coupled between the write bitline and ground and a second transistor coupled between the writebar bitline and ground. 
   
   
     3. The apparatus of  claim 2 , wherein the first and second transistors are negative channel transistors. 
   
   
     4. The apparatus of  1 , wherein the ground biased read control circuitry includes a transistor coupled between the read bitline and ground. 
   
   
     5. The apparatus of  claim 4 , wherein the transistor is a negative channel transistor. 
   
   
     6. The apparatus of  claim 1 , further comprising read bitline sense control circuitry to sense the value stored in the memory cell during read operations. 
   
   
     7. The apparatus of  claim 6 , wherein the read bitline sense control circuitry includes a transistor coupled between the read bitline and a voltage source node. 
   
   
     8. The apparatus of  claim 7 , wherein the transistor is a positive channel transistor. 
   
   
     9. The apparatus of  claim 1 , wherein the write bitline keeper includes a first inverter and a first transistor coupled between the write bitline and a predetermined voltage node and a second inverter and a second transistor coupled between the writebar bitline and the predetermined voltage node. 
   
   
     10. The apparatus of  claim 9 , wherein the first transistor and the second transistor are positive channel transistors. 
   
   
     11. An apparatus comprising
 a plurality of memory cells; 
 timing architecture circuitry to receive read and write enable signals and read and write memory addresses and to enable appropriate ones of the memory cells for reading or writing based thereon; 
 a data input latch to receive data and to activate a write bitline or a writebar bitline based on input data received, wherein the appropriate bitline is activated when writing is enabled; 
 ground biased write control circuitry to bias the write and writebar bitlines to ground when the timing architecture circuitry indicates writing is not enabled; 
 ground biased read control circuitry to bias a read bitline to ground when the timing architecture circuitry indicates reading is not enabled; and 
 a data output latch to output data read from the memory cells when a latch enable signal is activated. 
 
   
   
     12. The apparatus of  claim 11 , wherein the timing architecture circuitry includes
 a write enable latch to receive a signal indicating the apparatus is in write mode and to activate a write enable signal on a positive edge of a clock signal; 
 a write address decoder to receive a write address and to decode the write address and activate associated write wordlines on the positive edge of the clock signal; 
 low phase timing logic to activate write driver enable and write wordline enable signals during low phases of the clock while the apparatus is in write mode; and 
 write wordline activation circuitry to activate a write wordline based on the associated write wordline and the write wordline enable signal. 
 
   
   
     13. The apparatus of  claim 11 , wherein the timing architecture circuitry includes
 a read enable latch to receive a signal indicating the apparatus is in read mode and to activate a read enable signal on a positive edge of a clock signal; 
 a read address decoder to receive a read address and to decode the read address and activate associated read wordlines on the positive edge of the clock signal; and 
 read wordline activation circuitry to activate a read wordline based on the associated read wordline and the read enable signal. 
 
   
   
     14. The apparatus of  claim 11 , wherein
 the ground biased write control circuitry includes a first negative channel transistor coupled between the write bitline and ground and a second negative transistor coupled between the writebar bitline and ground; and 
 the ground biased read control circuitry includes a negative channel transistor coupled between the read bitline and ground. 
 
   
   
     15. The apparatus of  claim 11 , further comprising a write bitline keeper to maintain one of the write and writebar bitlines at a predetermined voltage during consecutive write cycles. 
   
   
     16. The apparatus of  claim 15 , wherein the write bitline keeper includes a first inverter and a first positive channel transistor coupled between the write bitline and a predetermined voltage node and a second inverter and a second positive channel transistor coupled between the writebar bitline and the predetermined voltage node. 
   
   
     17. The apparatus of  claim 11 , further comprising read bitline sense control circuitry to sense the value stored in the memory cell during read operations. 
   
   
     18. The apparatus of  claim 17 , wherein the read bitline sense control circuitry includes a positive transistor coupled between the read bitline and a predetermined voltage node. 
   
   
     19. The apparatus of  claim 17 , further comprising an inverter coupled between the read bitline sense control circuitry and the data output latch to trip if the signal read from the memory cell exceeds the threshold.