Method of manufacturing a semiconductor device having a plurality of memory and non-memory devices

Abstract

Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole.

1. A method comprising:
 simultaneously forming a first gate over a first device area and a second gate over a second device area of a semiconductor substrate, wherein the first gate includes spacers formed on and contacting sidewalls thereof; 
 depositing a PMD layer on the semiconductor substrate and patterning the PMD layer to form a first contact hole exposing only the first gate and the spacers; and 
 forming an insulating layer, a metal layer, and a third gate in the first contact hole over the first gate such that the insulating layer contacts the first gate and the spacers, the third gate being a control gate. 
 
   
   
     2. The method of  claim 1 , wherein forming the insulating layer, the metal layer, and the third gate comprises depositing a high dielectric constant material and first and second metallic materials over the semiconductor substrate and planarizing them to expose the PMD layer. 
   
   
     3. The method of  claim 2 , wherein the high dielectric constant material comprises Al 2 O 3 . 
   
   
     4. The method of  claim 2 , wherein the first metallic material comprises Ti or TiN. 
   
   
     5. The method of  claim 2 , wherein the second metallic material comprises W. 
   
   
     6. The method of  claim 1 , further comprising:
 patterning the PMD layer to form a second contact hole exposing the second gate, third contact holes in the first device area and fourth contact holes in the second device area; and 
 depositing a third metallic material over the semiconductor substrate and planarizing it such that the PMD layer is exposed, to form a contact in the second contact hole, the third contact holes and the fourth contact holes. 
 
   
   
     7. The method of  claim 6 , wherein the third gate comprises a metallic material substantially identical to a metallic material forming the contact. 
   
   
     8. The method of  claim 6 , wherein the third gate comprises a metallic material different from a material forming the contact. 
   
   
     9. The method of  claim 1 , further comprising forming a second PMD layer over the first device area and the second device area, patterning the PMD layer and the second PMD layer to form second contact holes in the second PMD layer over the second gate and third gate, and forming contacts within the second contact holes contacting and electrically connected to the second gate and the third gate, respectively. 
   
   
     10. The method of  claim 1 , wherein the insulating layer provides capacitance. 
   
   
     11. The method of  claim 1 , wherein the metal layer is configured to attach the third gate to the insulating layer. 
   
   
     12. A method comprising:
 simultaneously forming a first gate in a first region of a substrate and a second gate in a second region of the substrate, wherein the second gate include second spacers formed on and contacting sidewalls thereof; and then 
 forming a dielectric layer on the substrate including the first gate and the second gate; and then 
 forming a first contact hole in the dielectric layer exposing only the second gate and the second spacers; and then 
 forming an insulating layer composed of a high dielectric constant material in the contact hole and in contact with the dielectric layer, the second gate and the second spacers; and then 
 forming a barrier layer composed of a first metallic material on and contacting the insulating layer; and then 
 forming a third gate composed of a second metallic material on and contacting the barrier layer and exposing the dielectric layer, the insulating layer and the barrier layer. 
 
   
   
     13. The method of  claim 12 , further comprising, after forming the third gate:
 forming a plurality of second contact holes in the dielectric layer in the first region and a plurality of third contact holes in the dielectric layer in the second region; and then 
 forming a plurality of contacts composed of a third metallic material in the plurality of second contact holes and the plurality of third contact holes; and then 
 forming a plurality of interconnections composed of a fourth metallic material onthe dielectric layer and contacting the plurality of contacts, the third gate, the barrier layer and the insulating layer. 
 
   
   
     14. The method of  claim 13 , wherein the first metallic material comprises titanium, the second metallic material comprises tungsten, the third metallic material comprises tungsten and the fourth metallic material comprises aluminum or copper. 
   
   
     15. The method of  claim 13 , wherein the first metallic material and the third metallic material are the same material. 
   
   
     16. The method of  claim 12 , wherein the high dielectric constant material comprises Al 2 O 3 . 
   
   
     17. The method of  claim 12 , wherein the second gate comprises a floating gate and the third gate comprises a control gate. 
   
   
     18. A method comprising:
 simultaneously forming a first gate of a non-memory device and a second gate of a memory device on a substrate, wherein the second gate has second spacers formed on and contacting sidewalls thereof; and then 
 forming a dielectric layer on the substrate including the first gate, the second gate and the second spacers; and then 
 forming a first contact hole in the dielectric layer exposing the second gate and the second spacers; and then 
 forming an insulating layer composed of a high dielectric constant material in the contact hole and contacting the dielectric layer, the second gate and the second spacers, a barrier layer composed of a first metallic material on and contacting the insulating layer, and a third gate composed of a second metallic material on and contacting the barrier layer, wherein the barrier layer is formed after forming the insulating layer and the third gate is formed after forming the barrier layer; 
 forming a plurality of second contact holes in the dielectric layer; and then 
 forming a plurality of contacts composed of a third metallic material in the plurality of second contact holes, wherein the third metallic material is the same material as the first metallic material; and then 
 forming an interconnection composed of a fourth metallic material on the dielectric layer and contacting the third gate, the barrier layer and the insulating layer. 
 
   
   
     19. The method of  claim 18 , wherein the second gate comprises a floating gate and the third gate comprises a control gate. 
   
   
     20. The method of  claim 18 , wherein the first gate and the second gate are formed on different regions of the substrate.