Partial switch gate driver

Abstract

A power switch driver includes a top driver switch, a bottom driver switch, a driver node between them, and driver logic. The power switch driver can turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a lower second voltage level. The driver logic may include a pulse width generator programmer and a pulse width generator. The pulse width generator is controlled by the pulse width generator programmer and an input signal. Some power switch drivers include a feedback loop, coupled to the driver node and to the driver logic. The feedback loop may include a track-and-hold circuit, coupled to the driver node, to the pulse width generator through an error amplifier and to the input terminal.

1. A power switch driver comprising:
 a top driver switch coupled between a first voltage rail and a driver node; 
 a bottom driver switch coupled between the driver node and a second voltage rail; and 
 driver logic operationally coupled to the top driver switch and the bottom driver switch; 
 wherein the power switch driver is connectable to a power switch; and 
 wherein the power switch driver is operable to turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a second voltage level, wherein the second voltage level is lower than the first voltage level; 
 wherein the driver logic comprises:
 a pulse width generator programmer; 
 a pulse width generator coupled to the second voltage rail and having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal of the pulse width generator is coupled to the pulse width generator programmer, wherein the second input terminal of the pulse width generator is coupled to an input terminal, wherein the first output terminal of the pulse width generator is coupled to a gate of the top driver switch; 
 wherein the pulse width generator comprises:
 a comparator having a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal of the comparator being the first input terminal of the pulse width generator; 
 a ramp generator having an input terminal and an output terminal, the input terminal of the ramp generator being the second input terminal of the pulse width generator and the output terminal of the ramp generator being coupled to the inverting input terminal of the comparator; and 
 an AND gate having a first input terminal and a second input terminal, the first input terminal of the AND gate coupled to the output terminal of the comparator and the second input terminal of the AND gate coupled to the input terminal of the ramp generator. 
 
 
 
   
   
     2. The power switch driver of  claim 1 , wherein
 the power switch driver is connectable to the power switch by coupling a gate of the power switch to the driver node; and 
 coupling a source of the power switch to the second voltage rail. 
 
   
   
     3. The power switch driver of  claim 1 , wherein
 the power switch is one of an n-channel MOSFET, a p-channel MOSFET, bipolar transistor and an insulated gate bipolar transistor. 
 
   
   
     4. The power switch driver of  claim 1 , wherein
 one of the first and second input terminals is coupled to a gate of the bottom driver switch through an inverter. 
 
   
   
     5. The power switch driver of  claim 1 , wherein
 the pulse width generator programmer is a control voltage source. 
 
   
   
     6. The power switch driver of  claim 1 , further comprising:
 a feedback loop, coupled to the driver node and to the driver logic. 
 
   
   
     7. A power switch driver comprising:
 a top driver switch coupled between a first voltage rail and a driver node; 
 a bottom driver switch coupled between the driver node and a second voltage rail; 
 driver logic operationally coupled to the top driver switch and the bottom driver switch; 
 wherein the power switch driver is connectable to a power switch; and 
 wherein the power switch driver is operable to turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a second voltage level, wherein the second voltage level is lower than the first voltage level; 
 wherein the driver logic comprises:
 a pulse width generator programmer; and 
 a pulse width generator coupled to the second voltage rail and having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal of the pulse width generator is coupled to the pulse width generator programmer, wherein the second input terminal of the pulse width generator is coupled to an input terminal, wherein the first output terminal of the pulse width generator is coupled to a gate of the top driver switch; and 
 
 a feedback loop coupled to the driver node and to the driver logic, the feedback loop comprising a track-and-hold circuit; coupled to the driver node, to the pulse width generator through an error amplifier, and to the input terminal. 
 
   
   
     8. The power switch driver of  claim 7 , wherein
 the track-and-hold block is coupled to an inverting input terminal of the error amplifier; and 
 the pulse width generator programmer is coupled to a non-inverting input terminal of the error amplifier. 
 
   
   
     9. The power switch driver of  claim 7 , wherein the track-and-hold block comprises:
 a sensing terminal, coupled to the driver node; 
 a control terminal, coupled to the input terminal; 
 an output terminal; 
 a switch, coupled between the sensing terminal and the output terminal; 
 the switch comprising a gate coupled to the control terminal and controlled by an input signal; and 
 a memory capacitor, coupled to the output terminal. 
 
   
   
     10. A power switch driver circuit for driving a power switch, the power switch driver circuit comprising:
 a top driver switch and a bottom driver switch coupled at a driver node to the power switch; and 
 a pulse width generator programmer and a pulse width generator for providing pulse width modulation (PWM) control signals to at least one of the top driver switch and the bottom driver switch for driving the power switch, the pulse width generator comprising:
 a comparator having a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal of the comparator coupled to the pulse width generator programmer; 
 a ramp generator having an input terminal and an output terminal, the output terminal of the ramp generator being coupled to the inverting input terminal of the comparator; and 
 an AND gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the AND gate coupled to the output terminal of the comparator, the second input terminal of the AND gate coupled to the input terminal of the ramp generator, and the output terminal of the AND gate coupled to the top driver switch; 
 
 wherein the power switch driver circuit is operable to turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a second voltage level, wherein the second voltage level is lower than the first voltage level. 
 
   
   
     11. The power switch driver circuit of  claim 10 , wherein the power switch driver circuit is connectable to the power switch by coupling a gate of the power switch to the driver node and coupling a source of the power switch to the second voltage rail. 
   
   
     12. The power switch driver circuit of  claim 10 , wherein the power switch is one of an n-channel MOSFET, a p-channel MOSFET, bipolar transistor and an insulated gate bipolar transistor. 
   
   
     13. The power switch driver circuit of  claim 10 , wherein the pulse width generator programmer comprises a control voltage source. 
   
   
     14. The power switch driver of  claim 10 , comprising a feedback loop coupled to the driver node and to the pulse width generator. 
   
   
     15. The power switch driver of  claim 10 , comprising a track-and-hold circuit coupled to the driver node and to the pulse width generator through an error amplifier. 
   
   
     16. A power switch driver circuit for driving a power switch, the power switch driver circuit comprising:
 a top driver switch and a bottom driver switch coupled at a driver node to the power switch; 
 driver logic for providing control signals to the top driver switch and the bottom driver switch for driving the power switch at the driver node, the driver logic comprising:
 a pulse width generator programmer; and 
 a pulse width generator having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal of the pulse width generator is coupled to the pulse width generator programmer, wherein the second input terminal of the pulse width generator is coupled to an input terminal, wherein the first output terminal of the pulse width generator is coupled to the top driver switch; 
 wherein the pulse width generator programmer and the pulse width generator generate at least a portion of the control signals; and 
 
 a feedback loop for providing a feedback signal to the driver logic, the feedback loop comprising a track-and-hold circuit for tracking and holding a value of voltage at the driver node; 
 wherein the power switch driver circuit is operable to turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a second voltage level, wherein the second voltage level is lower than the first voltage level. 
 
   
   
     17. The power switch driver circuit of  claim 16 , wherein the power switch driver circuit is connectable to the power switch by coupling a gate of the power switch to the driver node. 
   
   
     18. The power switch driver circuit of  claim 16 , wherein the power switch is one of an n-channel MOSFET, a p-channel MOSFET, bipolar transistor and an insulated gate bipolar transistor. 
   
   
     19. The power switch driver circuit of  claim 16 , wherein the pulse width generator programmer comprises a control voltage source.