Insulated gate semiconductor device and method for manufacturing same

Abstract

In an insulated gate semiconductor device ( 1 ) having an N − type base region ( 11 ), P + type collector regions ( 12 ), P type base regions ( 13 ), and N + type emitter regions ( 14 ), an N + type collector-short region ( 15 ) which extends toward the N − type base region ( 11 ) farther than the P + type collector regions ( 12 ) is formed in the lower surface of the N − type base region ( 11 ), and a P + type semiconductor region ( 16 ) is formed between the N + type collector-short region ( 15 ) and the N − type base region ( 11 ).

1. An insulated gate semiconductor device, comprising:
 a first semiconductor region having a first conductivity type; 
 second semiconductor regions having a second conductivity type, formed in one principal surface of said first semiconductor region; 
 third semiconductor regions having the second conductivity type, formed in surface regions of the other principal surface of said first semiconductor region; 
 fourth semiconductor regions having the first conductivity type, formed in surface regions of said third semiconductor regions; 
 a first electrode electrically connected to said fourth semiconductor regions; 
 a control electrode disposed, via an insulating film, on the other principal surface between said first semiconductor region and said fourth semiconductor regions; and 
 a second electrode electrically connected to said second semiconductor regions, 
 wherein said insulated gate semiconductor device comprises; 
 a fifth semiconductor region having the first conductivity type, formed in the one principal surface of said first semiconductor region so as to be adjacent to said second semiconductor regions; and 
 a sixth semiconductor region having the second conductivity type, formed between said fifth semiconductor region and said first semiconductor region, said sixth semiconductor region formed such that at least a part of said fifth semiconductor region contacts said first semiconductor region. 
 
   
   
     2. The insulated gate semiconductor device according to  claim 1 ,
 wherein said sixth semiconductor region is formed between a side of said fifth semiconductor region closer to the other principal surface and said first semiconductor region. 
 
   
   
     3. The insulated gate semiconductor device according to  claim 1 ,
 wherein said fifth semiconductor region is formed so as to be more prominent than said second semiconductor regions. 
 
   
   
     4. The insulated gate semiconductor device according to  claim 1 ,
 wherein a width of said sixth semiconductor region is smaller than a width of said fifth semiconductor region. 
 
   
   
     5. The insulated gate semiconductor device according to clam  1 ,
 wherein concentration of an impurity of the second conductivity type in said sixth semiconductor region is 1×10 15  to 5×10 18  cm −3 . 
 
   
   
     6. The insulated gate semiconductor device according to  claim 1 ,
 wherein said fifth semiconductor region is formed so as not to face said third semiconductor regions. 
 
   
   
     7. The insulated gate semiconductor device according to  claim 1 ,
 wherein said first semiconductor region comprises a first region and second regions higher in impurity concentration than said first region, and said second regions are adjacent to said fifth semiconductor region. 
 
   
   
     8. The insulated gate semiconductor device according to  claim 1 ,
 wherein said sixth semiconductor region is electrically floating. 
 
   
   
     9. A method for manufacturing an insulated gate semiconductor device comprising: a first semiconductor region having a first conductivity type; second semiconductor regions having a second conductivity type, formed in one principal surface of said first semiconductor region; third semiconductor regions having the second conductivity type, formed in surface regions of the other principal surface of said first semiconductor region; fourth semiconductor region having the first conductivity type, formed in surface regions of said third semiconductor regions; a first electrode electrically connected to said fourth semiconductor regions a control electrode disposed, via an insulating film, on the other principal surface between said first semiconductor region and said fourth semiconductor regions; and a second electrode electrically connected to said second semiconductor regions, said method comprising:
 a step of forming a fifth semiconductor region having the first conductivity type in the one principal surface of said first semiconductor region so as to be adjacent to said second semiconductor regions; and 
 a step of forming a sixth semiconductor region having the second conductivity type, between said fifth semiconductor region and said first semiconductor region, said sixth semiconductor region formed such that at least a part of said fifth semiconductor region contacts said first semiconductor region. 
 
   
   
     10. The method for manufacturing the insulated gate semiconductor device according to  claim 9 ,
 wherein said sixth semiconductor region is formed so as to be electrically floating.