Apparatus and method for auto-zeroing a sampled comparator

Abstract

A comparator compares an input voltage and a reference voltage and generates an output based on the comparison. The comparator may receive the input voltage in a normal mode of operation. Voltage band circuitry provides first and second test voltages to the comparator. The test voltages define a band around the reference voltage. An integrator adjusts an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. The output of the comparator that is generated using the first test voltage could be generated during a first auto-zeroing cycle. The output of the comparator that is generated using the second test voltage could be generated during a second auto-zeroing cycle. This technique helps to maintain the offset of the comparator with the band around the reference voltage.

1. An apparatus comprising:
 a comparator operable to compare an input voltage and a reference voltage and to generate an output based on the comparison; 
 circuitry operable to provide a first test voltage and a second test voltage to the comparator, the test voltages defining a band around the reference voltage; and 
 an integrator operable to adjust an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. 
 
   
   
     2. The apparatus of  claim 1 , wherein:
 the first test voltage is larger than the reference voltage; and 
 the second test voltage is smaller than the reference voltage. 
 
   
   
     3. The apparatus of  claim 1 , wherein the circuitry comprises:
 a first switch operable to provide the first test voltage to an input of the comparator; 
 a second switch operable to provide the second test voltage to the input of the comparator; and 
 a third switch operable to provide the input voltage to the input of the comparator. 
 
   
   
     4. The apparatus of  claim 3 , wherein:
 the first and second switches are open, the third switch is closed, and the input voltage is provided to the comparator during a normal mode of operation; 
 the first switch is closed, the second and third switches are open, and the first test voltage is provided to the comparator during a first auto-zeroing cycle; and 
 the second switch is closed, the first and third switches are open, and the second test voltage is provided to the comparator during a second auto-zeroing cycle. 
 
   
   
     5. The apparatus of  claim 4 , wherein the integrator comprises:
 a first latch operable to sample the output of the comparator during the first auto-zeroing cycle; 
 a second latch operable to sample the output of the comparator during the second auto-zeroing cycle; and 
 a counter operable to increment or decrement a digital offset correction signal. 
 
   
   
     6. The apparatus of  claim 5 , wherein:
 the counter is operable to increment or decrement the digital offset correction signal based on an inverted output from one of the latches; and 
 the integrator further comprises combinatorial logic operable to prevent the counter from incrementing or decrementing when the non-inverted outputs from the latches are not equal. 
 
   
   
     7. The apparatus of  claim 5 , further comprising a digital-to-analog converter operable to convert the digital offset correction signal into an analog offset correction signal that is provided to the comparator. 
   
   
     8. The apparatus of  claim 5 , further comprising:
 a first delay element operable to delay a first control signal associated with the first switch and to provide the delayed first control signal to the first latch; 
 a second delay element operable to delay a second control signal associated with the second switch and to provide the delayed second control signal to the second latch; and 
 a third delay element operable to delay the delayed second control signal provided by the second delay element and to provide the twice-delayed second control signal to the counter. 
 
   
   
     9. The apparatus of  claim 1 , further comprising:
 a current source; and 
 a plurality of resistors coupled in series between the current source and ground, the resistors operable to generate the reference voltage, the first test voltage, and the second test voltage. 
 
   
   
     10. A system comprising:
 a signal source operable to provide an input voltage; and 
 circuitry for comparing the input voltage to a reference voltage, the circuitry comprising:
 a comparator operable to compare the input voltage and the reference voltage and to generate an output based on the comparison; 
 voltage band circuitry operable to provide a first test voltage and a second test voltage to the comparator, the test voltages defining a band around the reference voltage; and 
 an integrator operable to adjust an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. 
 
 
   
   
     11. The system of  claim 10 , wherein:
 the first test voltage is larger than the reference voltage; and 
 the second test voltage is smaller than the reference voltage. 
 
   
   
     12. The system of  claim 10 , wherein the voltage band circuitry comprises:
 a first switch operable to provide the first test voltage to an input of the comparator; 
 a second switch operable to provide the second test voltage to the input of the comparator; and 
 a third switch operable to provide the input voltage to the input of the comparator. 
 
   
   
     13. The system of  claim 12 , wherein:
 the first and second switches are open, the third switch is closed, and the input voltage is provided to the comparator during a normal mode of operation; 
 the first switch is closed, the second and third switches are open, and the first test voltage is provided to the comparator during a first auto-zeroing cycle; and 
 the second switch is closed, the first and third switches are open, and the second test voltage is provided to the comparator during a second auto-zeroing cycle. 
 
   
   
     14. The system of  claim 13 , wherein the integrator comprises:
 a first latch operable to sample the output of the comparator during the first auto-zeroing cycle; 
 a second latch operable to sample the output of the comparator during the second auto-zeroing cycle; and 
 a counter operable to increment or decrement a digital offset correction signal. 
 
   
   
     15. The system of  claim 14 , wherein:
 the counter is operable to increment or decrement the digital offset correction signal based on an inverted output from one of the latches; and 
 the integrator further comprises combinatorial logic operable to prevent the counter from incrementing or decrementing when the non-inverted outputs from the latches are not equal. 
 
   
   
     16. The system of  claim 14 , wherein the circuitry further comprises a digital-to-analog converter operable to convert the digital offset correction signal into an analog offset correction signal that is provided to the comparator. 
   
   
     17. The system of  claim 14 , wherein the circuitry further comprises:
 a first delay element operable to delay a first control signal associated with the first switch and to provide the delayed first control signal to the first latch; 
 a second delay element operable to delay a second control signal associated with the second switch and to provide the delayed second control signal to the second latch; and 
 a third delay element operable to delay the delayed second control signal provided by the second delay element and to provide the twice-delayed second control signal to the counter. 
 
   
   
     18. A method comprising:
 providing a first test voltage and a second test voltage to a comparator, the comparator operable to compare the test voltages to a reference voltage; 
 adjusting an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages; and 
 providing an input voltage to the comparator, the comparator operable to compare the input voltage and the reference voltage and to generate an output, the output based on the offset correction signal. 
 
   
   
     19. The method of  claim 18 , wherein adjusting the offset correction signal comprises:
 sampling, with a first latch, the output of the comparator generated using the first test voltage; 
 sampling, with a second latch, the output of the comparator generated using the second test voltage; 
 if the sampled outputs of both latches are equal, incrementing or decrementing a digital offset correction signal provided by a counter; and 
 converting the incremented or decremented digital offset correction signal into an analog offset correction signal that is provided to the comparator. 
 
   
   
     20. The method of  claim 19 , wherein:
 providing the first test voltage to the comparator comprises closing a first switch based on a first control signal; 
 providing the second test voltage to the comparator comprises closing a second switch based on a second control signal; 
 providing the input voltage to the comparator comprises closing a third switch based on a third control signal; and 
 the method further comprises:
 clocking the first latch with a delayed version of the first control signal; 
 clocking the second latch with a delayed version of the second control signal; and 
 clocking the counter with a twice-delayed version of the second control signal.