Programmable frequency multiplier

Abstract

A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2 n ×f (n=0, 1, 2, . . . ); a selector section configured to select a plurality of the doubled signals output from the frequency doubler section, and to output the plurality of the selected doubled signals as selected signals; and a frequency summation section configured to multiply the selected signals, and to output a multiplied signal having a frequency f out =f×(m 0 2 0 +m 1 2 1 + . . . +m k 2 k + . . . +m n 2 n ), wherein m k =0 or 1, and k=0, 1, . . . , n.

1. A programmable frequency multiplier device, comprising:
 a frequency doubler section configured to receive an input signal having a frequency f, and to output a plurality of doubled signals, each of the plurality of doubled signals having a frequency 2 n ×f (n=0, 1, 2, . . . ); 
 a selector section configured to select a plurality of the doubled signals output from the frequency doubler section, and to output the plurality of the selected doubled signals as selected signals; and 
 a frequency summation section configured to multiply the selected signals, and to output a multiplied signal having a frequency f out =f×(m 0 2 0 +m 1 2 1 + . . . +m k 2 k + . . . +m n 2 n ), wherein m k =0 or 1, and k=0, 1, . . . , n. 
 
   
   
     2. The programmable frequency multiplier device of  claim 1 ,
 wherein the frequency doubler section comprises n frequency doublers coupled in a cascaded chain, each of the frequency doublers constituting a h th  stage (h=1, 2, . . . , n), and 
 wherein each h th  frequency doubler at the h th  stage (h=1, 2, . . . , n) is configured to receive a signal having a frequency 2 (h−1) ×f and to output the doubled signal having a frequency 2 h ×f. 
 
   
   
     3. The programmable frequency multiplier device of  claim 2 , wherein at least one of the frequency doublers comprises:
 a first multiplier configured to receive a first component of a first input signal and a first component of a second input signal and to output a first multiplied signal; 
 a second multiplier configured to receive a second component of the first input signal and a second component of the second input signal and to output a second multiplied signal; 
 a third multiplier configured to receive the second component of the second input signal and the first component of the first input signal and to output a third multiplied signal; 
 a fourth multiplier configured to receive the first component of the first input signal and the second component of the second input signal and to output a fourth multiplied signal; 
 a first summer configured to receive the first and second multiplied signals and to output a first component of an output complex signal; and 
 a second summer configured to receive the third and fourth multiplied signals and to output a second component of the output complex signal. 
 
   
   
     4. The programmable frequency multiplier device of  claim 2 , wherein at least one of the frequency doublers comprises:
 a first summer having a first input port and a second input port and being configured to receive a first input signal at the first input port and at the second input port; and 
 a second summer having a first input port and a second input port and being configured to receive a second input signal at the first input port and the first input signal at the second input port. 
 
   
   
     5. The programmable frequency multiplier device of  claim 1 ,
 wherein the selector section comprises n+1 switches, each of the switches constituting a m th  stage (m=0, 1, 2, . . . , n), and 
 wherein each m th  switch at the m th  stage (m=0, 1, 2, . . . , n) is configured to receive the doubled signal having a frequency 2 m ×f from the frequency doubled section and a predetermined signal, and to select and output either of the doubled signal having a frequency 2 m ×f or the predetermined signal as a m th  selected signal. 
 
   
   
     6. The programmable frequency multiplier device of  claim 5 , wherein the predetermined signal is a DC signal. 
   
   
     7. The programmable frequency multiplier device of  claim 5 , wherein each of the switches is configured to be controlled by a programmable control signal. 
   
   
     8. The programmable frequency multiplier device of  claim 1 ,
 wherein the frequency summation section comprises n frequency combiners coupled in a cascaded chain, each of the frequency combiners constituting a h th  stage (h=1, 2, . . . , n), and 
 wherein at least one of the frequency combiners is configured to receive a first complex signal having a first frequency f 1  and a second complex signal having a second frequency f 2 , and to output a sum signal having a sum frequency f 1 +f 2 . 
 
   
   
     9. The programmable frequency multiplier device of  claim 8 , wherein at least one of the frequency combiners comprises:
 a first multiplier configured to receive a first component of a first input signal and a first component of a second input signal and to output a first multiplied signal; 
 a second multiplier configured to receive a second component of the first input signal and a second component of the second input signal and to output a second multiplied signal; 
 a third multiplier configured to receive the second component of the second input signal and the first component of the first input signal and to output a third multiplied signal; 
 a fourth multiplier configured to receive the first component of the first input signal and the second component of the second input signal and to output a fourth multiplied signal; 
 a first summer configured to receive the first and second multiplied signals and to output a first component of an output complex signal; and 
 a second summer configured to receive the third and fourth multiplied signals and to output a second component of the output complex signal. 
 
   
   
     10. A programmable frequency multiplier device, comprising:
 a first series of Complex Frequency Shifters (CFS's) being coupled in a cascaded chain having n (n=1, 2, 3, . . . ) stages, wherein a first CFS at a first stage of the first series is configured to receive an input signal having a frequency f and to output a first output signal in the first series having a frequency 2×f, and each of a h th  CFS at a h th  (h=2, 3, 4, . . . , n) stage of the first series is configured to receive a (h−1) th  output signal in the first series from a (h−1) th  CFS of the first series and to output a h th  output signal in the first series having a frequency 2 h ×f; 
 a series of switches comprising n+1 switches, each of the switches constituting a m th  stage (m=0, 1, 2, . . . , n), wherein a primary switch at a primary stage (m=0) is configured to select between the input signal and a predetermined signal and to output a primary selected signal, and wherein each of a m th  switch at a m th  stage (m=1, 2, 3, . . . , n) is configured to select the m th  output signal in the first series from the m th  CFS of the first series and the predetermined signal and to output a m th  selected signal; and 
 a second series of CFS's being coupled in a cascaded chain having n (n=1, 2, 3, . . . ) stages, wherein a first CFS at a first stage of the second series is configured to receive the primary selected signal from the primary switch and a first selected signal from a first switch and to output a first output signal in the second series, and wherein each of a h th  CFS at a h th  (h=2, 3, 4, . . . , n) stage of the second series is configured to receive a (h−1) th  output signal in the second series from a (h−1) th  CFS of the second series and a h th  selected signal from a h th  switch and to output a h th  output signal in the second series. 
 
   
   
     11. The programmable frequency multiplier device of  claim 10 , wherein at least one of the switches is configured to be controlled by a control bus and be programmable. 
   
   
     12. The programmable frequency multiplier device of  claim 10 , wherein at least one of the first series of CFS's comprises:
 a first summer having a first input port and a second input port and being configured to receive a first input signal at the first input port and at the second input port; and 
 a second summer having a first input port and a second input port and being configured to receive a second input signal at the first input port and the first input signal at the second input port. 
 
   
   
     13. The programmable frequency multiplier device of  claim 10 , wherein at least one of the first or second series of CFS's comprises:
 a first multiplier configured to receive a first component of a first input signal and a first component of a second input signal and to output a first multiplied signal; 
 a second multiplier configured to receive a second component of the first input signal and a second component of the second input signal and to output a second multiplied signal; 
 a third multiplier configured to receive the second component of the second input signal and the first component of the first input signal and to output a third multiplied signal; 
 a fourth multiplier configured to receive the first component of the first input signal and the second component of the second input signal and to output a fourth multiplied signal; 
 a first summer configured to receive the first and second multiplied signals and to output a first component of an output complex signal; and 
 a second summer configured to receive the third and fourth multiplied signals and to output a second component of the output complex signal. 
 
   
   
     14. A method of performing frequency multiplication, comprising:
 receiving a complex input signal, the complex input signal having a frequency f, the input signal corresponding to a 0 th  signal; 
 generating a n th  signal having a frequency 2 n ×f (n=1, 2, . . . ); 
 selecting between a h th  signal (h=0, 1, 2, . . . , n) having a frequency of 2 h ×f and a predetermined signal, and outputting the h th  selected signal; 
 multiplying all of the h th  selected signals (h=0, 1, 2, . . . , n); and 
 outputting an output signal having a frequency f out =f×(m 0 2 0 +m 1 2 1 + . . . +m k 2 k + . . . +m n 2 n ), wherein m k =0 or 1, and k=0, 1, . . . , n. 
 
   
   
     15. The method of performing frequency multiplication of  claim 14 ,
 wherein the generating a n th  signal having a frequency 2 n ×f (n=1, 2, . . . ) is performed by a series of frequency doublers being coupled in a cascaded chain and having n stages, and 
 wherein each of a h th  frequency doubler at the h th  stage (h=1, 2, . . . , n) outputs the h th  signal having a frequency 2 h ×f. 
 
   
   
     16. The method of performing frequency multiplication of  claim 14 ,
 wherein the multiplying the h th  selected signals (h=0, 1, 2, . . . , n) is performed by a series of frequency combiners being coupled in a cascaded chain, having n stages, 
 wherein a first frequency combiner at a first stage of the series of frequency combiners is configured to multiply a 0 th  selected signal and a first selected signal, and 
 wherein each of a h th  frequency combiner at the h th  stage (h=2, 3, . . . , n) of the series of frequency combiners is configured to multiply a (h−1) th  output signal from a (h−1) th  frequency combiner of the series of frequency combiners with the h th  selected signal. 
 
   
   
     17. The method of performing frequency multiplication of  claim 14 ,
 wherein the selecting between a h th  signal (h=0, 1, 2, . . . , n) having a frequency of 2 h ×f and a predetermined signal is performed by a series of switches, each of the switches constituting a m th  stage (m=0, 1, 2, . . . , n), and 
 wherein each of a m th  switch at the m th  stage (m=0, 1, 2, . . . , n) is configured to select and output one of the m th  signal having a frequency 2 m ×f (m=0, 1, 2, . . . , n) and a DC signal. 
 
   
   
     18. The method of performing frequency multiplication of  claim 17 , wherein the series of switches are configured to be controlled by a programmable control bus. 
   
   
     19. The method of performing frequency multiplication of  claim 15 , wherein at least one of the frequency doublers in the series of frequency doublers comprises:
 a first summer having a first input port and a second input port and being configured to receive a first input signal at the first input port and at the second input port; and 
 a second summer having a first input port and a second input port and being configured to receive a second input signal at the first input port and the first input signal at the second input port. 
 
   
   
     20. The method of performing frequency multiplication of  claim 15 , wherein at least one of the frequency doublers in the series of frequency doublers comprises:
 a first multiplier configured to receive a first component of a first input signal and a first component of a second input signal and to output a first multiplied signal; 
 a second multiplier configured to receive a second component of the first input signal and a second component of the second input signal and to output a second multiplied signal; 
 a third multiplier configured to receive the second component of the second input signal and the first component of the first input signal and to output a third multiplied signal; 
 a fourth multiplier configured to receive the first component of the first input signal and the second component of the second input signal and to output a fourth multiplied signal; 
 a first summer configured to receive the first and second multiplied signals and to output a first component of an output complex signal; and 
 a second summer configured to receive the third and fourth multiplied signals and to output a second component of the output complex signal.