Three-dimensional stack manufacture for integrated circuit devices and method of manufacture

Abstract

An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack. Solder pads on the interconnect substrates are reflowed to form a solder connection to the exposed vias, allowing complex interconnection between diverse points along the edge connectors of each substrate. In one embodiment, solder balls are reflowed on ball-grid-array pads at the top of the stack to provide external electrical connections.

1. A method of manufacturing a semiconductor assembly, said method comprising:
 mounting a first semiconductor element on a first substrate including electrical connections; 
 mounting a second semiconductor element on a second substrate including electrical connections; 
 stacking said first substrate on said second substrate to form a substrate stack; 
 removing a portion of said substrate stack to expose electrical connections along a side of said first substrate and a side of said second substrate; and 
 mounting an interconnect substrate on said sides of said first and second substrates to selectively connect exposed electrical connections between said first and second substrates. 
 
     
     
       2. The method of  claim 1 , wherein said method further includes securing said first substrate on said second substrate. 
     
     
       3. The method of  claim 2 , wherein said securing further includes securing said first substrate on said second substrate by injection molding. 
     
     
       4. The method of  claim 1 , wherein said stacking further includes placing a spacer between said first substrate and said second substrate to form said substrate stack. 
     
     
       5. The method of  claim 1 , wherein said removing further includes sawing a portion of said substrate stack. 
     
     
       6. The method of  claim 5 , wherein said sawing further includes sawing said substrate stack through a center axis of a plurality of vias within each of said first and second substrates. 
     
     
       7. The method of  claim 1 , wherein said method further includes forming a ball-grid array on said substrate stack.