Methods for fabricating ferroelectric memory devices

Abstract

A ferroelectric memory device includes a semiconductor substrate, ferroelectric capacitors, conductive patterns, and plate lines. The ferroelectric capacitors are arranged in rows and columns on the semiconductor substrate. The conductive patterns are arranged in even numbered and odd numbered rows. Each of the conductive patterns is on, and electrically connected to, a plurality of adjacent ones of the ferroelectric capacitors. The plate lines are in rows that extend along even numbered and odd numbered columns. The plate lines in the even numbered columns are electrically connected to at least two of the conductive patterns in the even numbered rows and are electrically isolated from the conductive patterns in the odd numbered rows. The plate lines in the odd numbered columns are electrically connected to at least two of the conductive patterns in the odd numbered rows and are electrically isolated from the conductive patterns in the even numbered rows.

1. A method for fabricating a ferroelectric memory device comprising the steps of:
 forming a lower insulation layer on a semiconductor substrate; 
 forming ferroelectric capacitors in rows and columns on the lower insulation layer; 
 forming conductive patterns, each electrically connected to a plurality of the ferroelectric capacitors that are adjacent along a row; 
 forming an upper insulation layer on the semiconductor substrate, wherein the upper insulating layer includes via holes; and 
 forming columns of plate lines, wherein each of the plate lines is electrically connected through the via holes in the upper insulation layer to the conductive patterns, and wherein at least two of the plate lines are on each of the conductive patterns. 
 
   
   
     2. The method of  claim 1 , wherein forming conductive patterns comprises:
 forming a supporting insulation layer on the lower insulation layer that covers the ferroelectric capacitors; 
 planarizing the supporting insulation layer to expose a top of the ferroelectric capacitors; 
 forming a conductive layer on the supporting insulation layer and the top of the ferroelectric capacitors; and 
 patterning the conductive layer to form the conductive patterns. 
 
   
   
     3. The method of  claim 1 , wherein forming conductive patterns comprises: forming an insulation layer on the lower insulation layer covering the ferroelectric capacitors;
 patterning the insulating layer to forming contact holes that expose the ferroelectric capacitors; 
 forming a conductive layer on the insulation layer and in the contact holes; and patterning the conductive layer to form conductive patterns. 
 
   
   
     4. The method of  claim 1 , wherein:
 each of the conductive patterns is electrically connected to 4*2 ferroelectric capacitors arranged in two rows and four columns; 
 two of the plate lines are on each of the conductive patterns; 
 the plate lines in odd numbered columns are electrically connected to the conductive patterns in odd numbered rows; and 
 the plate lines in even numbered columns are electrically connected to the conductive patterns in even numbered rows. 
 
   
   
     5. The method of  claim 1 , wherein:
 each of the conductive patterns is electrically connected to a top of four of the ferroelectric capacitors along a row; 
 four of the plate lines are on each of the conductive patterns; and 
 the plate lines in the 4*(k−1)+i columns are electrically connected to the conductive patterns in the 4*(k−1)+i rows, wherein k is natural number and i is in a range from 1 to 4. 
 
   
   
     6. The method of  claim 1 , wherein forming the upper insulation layer comprises forming a first and a second upper insulation layer, and further comprising forming a plurality of main word lines on the first upper insulating layer and parallel to the plate lines, wherein the second upper insulating layer is formed on the first upper insulating layer and the plate lines. 
   
   
     7. The method of  claim 1 , further comprising forming a hydrogen barrier layer on the ferroelectric capacitors. 
   
   
     8. A method for fabricating a ferroelectric memory device comprising the steps of:
 forming a lower insulation layer on a semiconductor substrate; 
 forming a supporting insulation layer on the lower insulation layer; 
 patterning the supporting insulation layer to form trenches arranged in rows and columns; 
 forming bottom electrodes in the trenches; 
 forming a ferroelectric layer on the bottom electrodes; 
 forming an upper electrode layer on the ferroelectric layer; 
 patterning the upper electrode layer to form upper electrodes arranged in rows and columns, and wherein each of the upper electrodes is on at least a row of four adjacent bottom electrodes; 
 forming an upper insulation layer; and 
 forming a plurality of columns of plate lines, wherein each of the plate lines is electrically connected to at least one of the upper electrodes through the upper insulation layer, and wherein at least two of the plate lines are on each of the upper electrodes. 
 
   
   
     9. The method of  claim 8 , wherein:
 each of the upper electrodes is on two rows of four of the bottom electrodes; 
 two of the plate lines are on each of the upper electrodes; 
 the plate lines in odd numbered columns are electrically connected to the upper electrodes in odd numbered rows; and 
 the plate lines in even numbered columns are electrically connected to the upper electrodes in even numbered rows. 
 
   
   
     10. The method of  claim 8 , wherein:
 each of the upper electrodes is on a row of four of the bottom; 
 four of the plate lines are on each of the upper electrodes; and 
 the plate lines in the 4*(k−1)+i columns are electrically connected to the upper electrodes in the 4*(k−1)+i rows, wherein k is natural number and i is in a range from 1 to 4.