Circuits with state circuitry having cross connected control inputs

Abstract

Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

1. A system comprising:
 A. a first circuit having a serial data input, a serial data output, a clock input, and a mode select input, the first circuit including state circuitry responsive to signals received on the clock input and mode select input for the first circuit to remain in an idle state where no data communication occurs and to enter a communication state where data is communicated between the serial data input and serial data output, with the serial data input, or with the serial data output; 
 B. a second circuit having a serial data input, a serial data output, a clock input, and a mode select input, the second circuit including state circuitry responsive to signals received on the clock input and mode select input for the second circuit to remain in an idle state where no data communication occurs and to enter a communication state where data is communicated between the serial data input and serial data output, with the serial data input, or with the serial data output; 
 C. a first lead connected to the clock input of the first circuit and the mode select input of the second circuit; and 
 D. a second lead connected to the clock input of the second circuit and the mode select lead of the first circuit. 
 
   
   
     2. The system of  claim 1  in which the state circuitry of the first circuit is a test access port according to standard IEEE 1149.1. 
   
   
     3. The system of  claim 1  in which the state circuitry of the second circuit is a test access port according to standard IEEE 1149.1. 
   
   
     4. The system of  claim 1  in which the state circuitry of the first circuit is a test access port according to standard IEEE 1149.1, and in which the state circuitry of the second circuit is a test access port according to standard IEEE 1149.1. 
   
   
     5. The system of  claim 1  in which the idle state of the state circuitry of the first and second circuits corresponds to an RTIDLE state defined in standard IEEE 1149.1. 
   
   
     6. The system of  claim 1  in which the communication state of the state circuitry of the first and second circuits corresponds to an DR-Shift state defined in standard IEEE 1149.1. 
   
   
     7. The system of  claim 1  in which the communication state of the state circuitry of the first and second circuits corresponds to an IR-Shift state defined in standard IEEE 1149.1.