Split embedded DRAM processor

Abstract

A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

1. An embedded DRAM coprocessor formed on a first silicon substrate, comprising:
 an interface adapted for coupling to a processor, the processor being formed on a second silicon substrate; 
 a memory for holding instructions; 
 a set of one or more functional units; 
 an array of embedded DRAM; and 
 control logic responsive to a command sent via the interface from the processor, the control logic operative to fork and execute an execution thread in support of a multithreaded program executing on the processor.