In system analysis and compensation for a digital PWM controller

Abstract

A system for analyzing the operation of a switching power converter includes a digital controller for receiving an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generating switching control signals to control the operation of the power supply to regulate the output DC voltage to said output voltage level. At least one portion of a control loop within the digital controller may be switched into the control loop in a first mode of operation and out of the control loop in a second mode of operation. A microcontroller emulates the operation of the at least one portion of the control loop during the second mode of operation.

1. A system for analyzing an operation of a switching power converter, comprising:
 a digital controller for receiving an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generating switching control signals to control the operation of the switching power converter to regulate the output DC voltage to said desired output voltage level, the digital controller including at least one portion of a control loop of the digital controller, the at least one portion of the control loop generating a signal in a first mode of operation; 
 a microcontroller for emulating an operation of the at least one portion of the control loop during a second mode of operation and generating a synthesized version of the original signal; and 
 wherein the at least one portion of the control loop of the digital controller is switched into the control loop in a first mode of operation and the microcontroller is switched into the control loop in the second mode of operation to perform the operation of the at least one portion of the control loop. 
 
     
     
       2. The system of  claim 1 , wherein a second portion of the control loop may be switched out of the control loop in a third mode of operation, the second portion of the control loop generating a second signal. 
     
     
       3. The system of  claim 2 , wherein the microcontroller is switched into the control loop and emulates an operation of the second portion of the control loop during the third mode of operation. 
     
     
       4. The system of  claim 1 , wherein the digital controller further comprises:
 a differential analog-to-digital converter (ADC) for receiving the analog signal and the desired output voltage level and converting the difference therebetween to a digital error signal; 
 a digital compensator for processing of the digital error signal to compensate for loop phase offset to provide a compensated digital error signal; 
 a pulse width modulator for generating said switching control signals as a function of said a compensated digital error signal; 
 a first multiplexer connected to the output of the differential analog-to-digital converter for providing the digital error signal to the digital compensator in a first mode of operation and for providing the digital error signal to a second output in a second mode of operation; 
 a second multiplexer connected to an input of the pulse width modulator for providing the compensated digital error signal to the pulse width modulator in the first mode of operation and providing a synthesized compensated digital error signal from the microcontroller to the pulse width modulator in the second mode of operation. 
 
     
     
       5. The system of  claim 4 , wherein the first and the second multiplexer enter the first and the second modes of operation responsive to control signals from the microcontroller. 
     
     
       6. The system of  claim 4 , wherein the microcontroller includes an interface for providing access to the voltage error signals received in the microcontroller and the synthesized compensated digital error signal generated in the microcontroller. 
     
     
       7. The system of  claim 4 , wherein the microcontroller stores the received voltage error signals and the generated synthesized compensated digital error signals. 
     
     
       8. The system of  claim 4 , wherein the microcontroller combines a generated reference compensated digital error signal with a software generated sinusoidal signal to generate the synthesized compensated digital error signal. 
     
     
       9. The system of  claim 4 , wherein said microcontroller is operable to change parameters controlling operation of the digital controller as a result of analysis of the received voltage error signals and the generated synthesized compensated digital error signals. 
     
     
       10. The system of  claim 4 , wherein the first multiplexer connected to the output of the differential analog-to-digital converter provides a synthesized digital error signal to the compensator during a third mode of operation and the second multiplexer connected to an input of the pulse width modulator provides the compensated digital error signal to the microcontroller during the third mode of operation. 
     
     
       11. The system of  claim 10 , wherein the microcontroller receives the compensated digital error signal and models operation of the remaining components of the digital controller and an associated power supply to generate the synthesized digital error signal. 
     
     
       12. A system for analyzing an operation of a switching power converter, comprising:
 a differential analog-to-digital converter (ADC) for receiving an analog signal representing the output DC voltage of the power converter and a reference output voltage level and converting the difference therebetween to a digital error signal; 
 a digital compensator for processing of the digital error signal to compensate for loop phase offset to provide a compensated digital error signal in a first mode of operation; 
 a microcontroller emulating operation of the digital compensator responsive to the digital error signal to generate a synthesized compensated digital error signal during a second mode of operation; 
 a pulse width modulator for generating switching control signals for controlling operation of the switching power converter to provide a regulated output voltage responsive to the compensated digital error signal in the first mode of operation and responsive to the synthesized compensated digital error signal in the second mode of operation; 
 a first multiplexer connected to the output of the differential analog-to-digital converter for providing the digital error signal to the digital compensator in the first mode of operation and for providing the digital error signal to the microcontroller in the second mode of operation; and 
 a second multiplexer connected to an input of the pulse width modulator for providing the compensated digital error signal to the pulse width modulator in the first mode of operation and providing the synthesized compensated digital error signal to the pulse width modulator in the second mode of operation. 
 
     
     
       13. The system of  claim 12 , wherein the first and the second multiplexers enter the first and the second modes of operation responsive to control signals from the microcontroller. 
     
     
       14. The system of  claim 12 , wherein the microcontroller includes an interface for providing access to the voltage error signals received in the microcontroller and the synthesized compensated digital error signal generated in the microcontroller. 
     
     
       15. The system of  claim 12 , wherein the microcontroller stores the received voltage error signals and the generated synthesized compensated digital error signals. 
     
     
       16. The system of  claim 12 , wherein the microcontroller combines a generated reference compensated digital error signal with a software generated sinusoidal signal to generate the synthesized compensated digital error signal. 
     
     
       17. The system of  claim 12 , wherein said microcontroller is operable to change parameters controlling operation of the digital controller as a result of analysis of the received voltage error signals and the generated synthesized compensated digital error signals. 
     
     
       18. The system of  claim 12 , wherein the first multiplexer connected to the output of the differential analog-to-digital converter provides a synthesized digital error signal to the compensator during a third mode of operation and the second multiplexer connected to an input of the pulse width modulator provides the compensated digital error signal to the microcontroller during the third mode of operation. 
     
     
       19. The system of  claim 18 , wherein the microcontroller receives the compensated digital error signal and models operation of the remaining components of the digital controller and an associated power supply to generate the synthesized digital error signal. 
     
     
       20. A method for analyzing an operation of a switching power converter, comprising the steps of:
 switching at least one portion of a control loop of a digital controller of the switching power converter into the control loop and a microprocessor out of the control loop in a first mode of operation; and 
 generating a control signal using the at least one portion of the control loop in the first mode of operation; 
 switching the at least one portion of the control loop of the digital controller of the switching power converter out of the control loop and the microprocessor into the control loop in a second mode of operation; and 
 emulating in the microcontroller the operation of the at least one portion of the control loop to generate a synthesized control signal during the second mode of operation. 
 
     
     
       21. The method of  claim 20 , wherein the steps of switching further comprises the step of switching between the first mode and the second mode of operation responsive to control signals from the microcontroller. 
     
     
       22. The method of  claim 20 , wherein the step of emulating further comprises the steps of:
 receiving an error signal from the control loop; and 
 generating a synthesized compensated digital error signal responsive to the received error signal. 
 
     
     
       23. The method of  claim 22  further including the step of storing the voltage error signals received from the control loop and the generated synthesized compensated digital error signals. 
     
     
       24. The method of  claim 22 , wherein the step of generating further comprises the step of combining the generated reference compensated digital error signal with a software generated sinusoidal signal to generate the synthesized compensated digital error signal. 
     
     
       25. The method of  claim 20 , wherein the step of emulating further comprises the steps of altering parameters controlling operation of the at least one portion of the control loop. 
     
     
       26. The method of  claim 20 , further comprising the step of switching a second portion of the control loop out of the control loop in a third mode of operation. 
     
     
       27. The method of  claim 20 , wherein the step of emulating further comprises the step of emulating an operation of the second portion of the control loop during the third mode of operation.