Semiconductor device test method using an evaluation LSI

Abstract

An evaluation LSI includes a noise generation circuit generating a controlled amount of noise controlled from outside of the LSI, and a delay measurement circuit measuring a signal delay of a delay circuit influenced by the noise. The relationship between the amount of noise and the signal delay is determined. A device-under-test (DUT) LSI includes a functional circuit and a delay circuit having a signal delay influenced by the operation of the functional test. By evaluating the signal delay of the delay circuit in the DUT LSI, the amount of noise therein is estimated based on the determined relationship.

1. A method for testing a semiconductor device comprising:
 determining a relationship between an amount of noise generated in a noise generation circuit and a signal delay of a first delay circuit measured by a first delay measurement circuit in an evaluation semiconductor device (LSI), said noise generation circuit capable of generating a controlled amount of noise controlled from outside of said evaluation LSI, said first delay circuit having a delay time influenced by noise generated by said noise generation circuit; 
 measuring a signal delay of a second delay circuit by using a second delay measurement circuit in a device-under-test (DUT) LSI having a functional circuit upon operation of said functional circuit of said DUT LSI, said second delay circuit having a signal delay influenced by said functional circuit, said DUT LSI and said evaluation LSI being manufactured in a common process condition: and 
 evaluating an amount of noise generated in said DUT LSI based on said relationship determined in said determining step and said signal delay detected by said second delay measurement circuit. 
 
   
   
     2. The method according to  claim 1 , wherein an operation voltage of said evaluation LSI is equal to an operation voltage of said DUT LSI. 
   
   
     3. The method according to  claim 1 , wherein said first and second delay measurement circuits include therein said first and second delay circuits, respectively. 
   
   
     4. The method according to  claim 1 , wherein each of said first and second delay circuits includes a plurality (N) of cascaded delay gates, wherein each of said first and second delay measurement circuit includes a test signal generation block for feeding a test signal to a corresponding one of said first and second delay circuits, and a plurality (N) of latch gates each receiving an output from a corresponding one of said cascaded delay gates, and wherein said signal delay measuring step includes the steps of feeding said test signal from said test signal generation circuit to said second delay circuit, and judging outputs of said latch gates latching outputs of respective said delay gates after a specified time length elapsed since the time of said test signal feeding. 
   
   
     5. The evaluation LSI measured by the method according to  claim 1 , wherein a plurality of said first delay measurement circuit is provided for a single said noise generation circuit. 
   
   
     6. The DUT LSI measured by the method according to  claim 1 , wherein a plurality of said second delay measurement circuit is provided for a single said functional circuit. 
   
   
     7. A method for testing a clock signal, comprising:
 generating a test signal in response to a first clock pulse of the clock signal, to feed said test signal to first and second latch gates through data terminals thereof after providing first and second delays, respectively, to said test signal; 
 feeding a second clock pulse of the clock signal succeeding to said first clock pulse to said first and second latch gates through control terminals thereof, thereby allowing said first and second latch gates to latch said test signal delayed by said first and second delays, respectively; and 
 investigating outputs of said first and second latch gates to judge pass or fail for an oscillation period of the clock signal. 
 
   
   
     8. A semiconductor device comprising:
 a test signal generation circuit for receiving a first clock pulse of a clock signal to generate a test signal; 
 first delay gate for providing a first delay to said test signal, said first delay corresponding to an allowable shortest period of said clock signal; 
 a second delay gate for providing a second delay to said test signal, said second delay corresponding to a difference between an allowable longest period of said clock signal and said allowable shortest signal; 
 a first latch gate for latching an output of said first delay gate at a timing of a second clock pulse of said clock signal succeeding to said first clock pulse; 
 a second latch gate for latching an output of said second delay gate at the timing of said second clock pulse; and 
 a judgement circuit for judging a period of said clock signal based on outputs of said first and second latch gates. 
 
   
   
     9. The semiconductor device according to  claim 8 , further comprising:
 a third delay gate for providing a third delay to said test signal, said third delay corresponding to half said second delay; and 
 a third latch gate for latching an output of said third delay gate at the timing of said second clock pulse.