Low resistance T-shaped ridge structure

Abstract

A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge section is defined in the overgrowth layer and portions of the sacrificial layer are removed to define a shank section in the overgrowth layer under the ridge section. The ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section.

1. A method, comprising:
 defining a void in a sacrificial layer proximate to an active layer with a first etching substance reactive with the sacrificial layer, wherein the first etching substance comprises a mixture of H 2 SO 4 , H 2 O 2 , and H 2 O; 
 forming an overgrowth layer in the void and over portions of the sacrificial layer adjacent to the void, wherein the overgrowth layer comprises one of InP or AlGaAs; 
 defining a ridge section in the overgrowth layer with a second etching substance reactive with the overgrowth layer and substantially non-reactive with the sacrificial layer, wherein the second etching substance comprises a mixture of hydrochloric acid (HCl) and phosphoric acid (H 3 PO 4 ; and 
 removing portions of the sacrificial layer to define a shank section in the overgrowth layer under the ridge section, the ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section. 
 
     
     
       2. The method of  claim 1 , further comprising forming an etch stop layer between the active layer and the sacrificial layer, the etch stop layer being non-reactive with the first etching substance. 
     
     
       3. The method of  claim 1  wherein removing portions of the sacrificial layer to define the shank section in the overgrowth layer comprises etching away the portions of the sacrificial layer with the first etching substance. 
     
     
       4. The method of  claim 1 , further comprising forming a planarization layer around the shank section and the ridge section of the overgrowth layer, the planarization layer comprising a polymer. 
     
     
       5. The method of  claim 4 , further comprising forming a conductive contact on top of the ridge section, the conductive contact to couple the electrical interconnects to the ridge section. 
     
     
       6. The method of  claim 1  wherein the overgrowth layer comprises a P-doped semiconductor material and the active layer comprises an intrinsic semiconductor material. 
     
     
       7. The method of  claim 6  wherein the intrinsic semiconductor comprises one of InGaAsP, InGaAs, or GaAs. 
     
     
       8. The method of  claim 1  wherein the ridge and shank sections of the overgrowth layer form a substantially T-shaped ridge structure. 
     
     
       9. The method of  claim 6 , further comprising forming the sacrificial layer over an N-doped substrate layer, wherein the shank section of the overgrowth layer, the active layer, and the N-doped substrate layer form a P-I-N junction. 
     
     
       10. A method, comprising:
 defining a void in a sacrificial layer proximate to an active layer with a first etching substance reactive with the sacrificial layer; 
 forming an overgrowth layer in the void and over portions of the sacrificial layer adjacent to the void; 
 defining a ridge section in the overgrowth layer with a second etching substance reactive with the overgrowth layer and substantially non-reactive with the sacrificial layer; and 
 removing portions of the sacrificial layer to define a shank section in the overgrowth layer under the ridge section, the ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section. 
 
     
     
       11. The method of  claim 10  wherein defining the void in the sacrificial layer comprises etching the sacrificial layer. 
     
     
       12. The method of  claim 10 , further comprising forming an etch stop layer between the active layer and the sacrificial layer, the etch stop layer being non-reactive with the first etching substance. 
     
     
       13. The method of  claim 10  wherein removing portions of the sacrificial layer to define the shank section in the overgrowth layer comprises etching away the portions of the sacrificial layer with the first etching substance. 
     
     
       14. The method of  claim 10 , further comprising forming a planarization layer around the shank section and the ridge section of the overgrowth layer, the planarization layer comprising a polymer. 
     
     
       15. The method of  claim 14 , further comprising forming a conductive contact on top of the ridge section, the conductive contact to couple the electrical interconnects to the ridge section. 
     
     
       16. The method of  claim 10  wherein the overgrowth layer comprises a P-type semiconductor material and the active layer comprises an intrinsic semiconductor material. 
     
     
       17. The method of  claim 16  wherein the P-type semiconductor material comprises one of InP and AIGaAs, and wherein the intrinsic semiconductor comprises one of InGaAsP, InGaAs, and GaAs. 
     
     
       18. The method of  claim 17  wherein the first etching substance comprises a mixture of at least two of H 2 SO 4 , H 2 O 2 , and H 2 O, and wherein the second etching substance comprises a mixture of hydrochloric acid (HCl) and phosphoric acid (H 3 PO 4 ). 
     
     
       19. The method of  claim 10  wherein the ridge and shank sections of the overgrowth layer form a substantially T-shaped ridge structure. 
     
     
       20. A method, comprising:
 defining a void in a sacrificial layer proximate to an active layer with a first etching substance reactive with the sacrificial layer; 
 forming an overgrowth layer in the void and over portions of the sacrificial layer adjacent to the void; 
 defining a ridge section in the overgrowth layer with a second etching substance reactive with the overgrowth layer and substantially non-reactive with the sacrificial layer; 
 removing portions of the sacrificial layer to define a shank section in the overgrowth layer under the ridge section, the ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section; and 
 forming a planarization layer around the shank section and the ridge section of the overgrowth layer, the planarization layer comprising a polymer. 
 
     
     
       21. The method of  claim 20 , further comprising forming an etch stop layer between the active layer and the sacrificial layer, the etch stop layer being non-reactive with the first etching substance. 
     
     
       22. The method of  claim 21  wherein removing portions of the sacrificial layer to define the shank section in the overgrowth layer comprises etching away the portions of the sacrificial layer with the first etching substance. 
     
     
       23. The method of  claim 20 , further comprising forming a conductive contact on top of the ridge section, the conductive contact to couple the electrical interconnects to the ridge section. 
     
     
       24. The method of  claim 20  wherein the overgrowth layer comprises a P-type semiconductor material and the active layer comprises an intrinsic semiconductor material. 
     
     
       25. The method of  claim 20  wherein the ridge and shank sections of the overgrowth layer form a substantially T-shaped ridge structure.