Circuit element

Abstract

A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (V DD ) and lower voltage level (V SS ), in such a way that the paired transistors operate in subthreshold. N input terminals (X 1 , X 2 . . . X N ) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.

1. Circuit element, comprising:
 N pairs of transistor units, each pair including a first (MP) and a second (MN) complementary transistor unit with at least four nodes, where the first transistor unit includes
 a first node, which is connected to an upper (V DD ) voltage level, 
 a second node connected to the second node of a complementary transistor unit, 
 an input node that controls the current through, and the voltage over the first and second node, 
 a control input node that controls the current/voltage characteristics of the transistor unit, and 
 
 the second transistor unit includes
 a first node, which is connected to a lower (V SS ) voltage level, 
 a second node connected to the second node of a complementary transistor unit, 
 an input node that controls the current through, and the voltage over the first and second node, 
 a control input node that controls the current/voltage characteristics of the transistor unit, 
 
 where the second nodes of the respective paired transistor units also are connected to each other, and the upper and lower voltage levels (V DD , V SS ) are such that the transistor units operate in subthreshold, 
 N input terminals (X 1 , X 2 , . . . X N ) connected to input nodes of the respective paired transistor units, 
 an output terminal (CN) connected to input the interconnected second nodes of the paired transistor units, and 
 at least one of the following:
 a control terminal (BP) connected to the control input nodes of the first transistor units, of the N paired transistors, 
 a control terminal (BN) connected to the control input nodes of the second transistor units, of the N paired transistors, 
 
 where N is an integer. 
 
   
   
     2. Circuit element according to  claim 1 , characterized in that the first transistor units are PMOS transistors, and the second transistors are NMOS transistors. 
   
   
     3. Circuit element according to  claim 1 , characterized in that the circuit element can be reconfigured in real time, between a logic NAND-function, a logic NOR-function, and a CARRY′-function, by a change in the voltage level of at least one of the control terminals (BN, BP). 
   
   
     4. Circuit element according to  claim 1 , characterized in that 2≦N≦8, preferably 2≦N≦4. 
   
   
     5. Threshold element circuit with full adder function, characterized in that the circuit comprises two circuit elements according to  claim 1 , in which circuit elements N is 3, where the output terminal (CN) of the first circuit element is connected to the control terminal (BP) for the PMOS well terminals of the second circuit element, and where the first output, in the form of the carry terminal (C), is connected to the second nodes of a pair of transistor units, where the input terminal of this transistor unit pair is connected to the output terminal (CN) of the first circuit element, and where the second output, in the form of the sum terminal (S), is connected to the second nodes of a pair of transistor units, where the input terminal of this transistor unit pair is connected to the output terminal (SN) of the second circuit element.