Method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation

Abstract

The present invention is directed to a method and apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation. Addresses may be provided to multiplexers through configuration pins. The input ports of the multiplexers may be connected to interface pins of the pre-diffused IP blocks, and the output ports of the multiplexers may be connected to I/O pins which provide input and output to the semiconductor device. Through controlling the signals on the configuration pins and thus the outputs of multiplexers, any single pre-diffused IP blocks or any combination of the pre-diffused IP blocks in the semiconductor device may be exposed through corresponding I/O pins for prototyping.

1. A method for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation, comprising:
 connecting interface pins of at least two pre-diffused IP blocks in a semiconductor device to input ports of a multiplexer, wherein pre-diffused IP blocks are IP blocks in said semiconductor device whereon dopant has been deposited prior to diffusion; 
 connecting an output port of said multiplexer to an I/O pin of said semiconductor device; 
 providing an address to said multiplexer through a configuration pin of said semiconductor device to select which of said interface pins is actually connected to said I/O pin; and 
 connecting said I/O pin to a reusable field programmable device so that a pre-diffused IP block having said selected interface pin is selected for prototyping. 
 
     
     
       2. The method of  claim 1 , wherein said multiplexer has two input ports. 
     
     
       3. The method of  claim 1 , wherein said multiplexer has at least three input ports. 
     
     
       4. The method of  claim 1 , wherein said reusable field programmable device is a field programmable gate array. 
     
     
       5. The method of  claim 1 , wherein said reusable field programmable device is a programmable Logic device. 
     
     
       6. An apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation, comprising:
 a multiplexer; 
 means for connecting interface pins of at least two pre-diffused IP blocks in a semiconductor device to input ports of a multiplexer, wherein pre-diffused IP blocks are IP blocks in said semiconductor device whereon dopant has been deposited prior to diffusion; 
 means for connecting an output port of said multiplexer to an I/O pin of said semiconductor device; 
 means for providing an address to said multiplexer through a configuration pin of said semiconductor device to select which of said interface pins is actually connected to said I/O pin; and 
 means for connecting said I/O pin to a reusable field programmable device so that a pre-diffused IP block having said selected interface pin is selected for prototyping. 
 
     
     
       7. The apparatus of  claim 6 , wherein said multiplexer has two input ports. 
     
     
       8. The apparatus of  claim 6 , wherein said multiplexer has at least three input ports. 
     
     
       9. The apparatus of  claim 6 , wherein said reusable field programmable device is a field programmable gate array. 
     
     
       10. The apparatus of  claim 6 , wherein said reusable field programmable device is a programmable logic device. 
     
     
       11. An apparatus for exposing pre-diffused IP blocks in a semiconductor device for prototyping based on hardware emulation, comprising:
 pre-diffused IP blocks in a semiconductor device, wherein pre-diffused IP blocks are IP blocks in said semiconductor device whereon dopant has been deposited prior to diffusion, 
 I/O pins of said semiconductor device for providing input and output to said semiconductor device; 
 a multiplexer communicatively coupled to interface pins of said pre-diffused IP blocks and one of said I/O pins; 
 a configuration pin of said semiconductor device for providing an address to said multiplexer to select which of said interface pins is connected to said I/O pin; and 
 a reusable field programmable device connected to said I/O pin for prototyping. 
 
     
     
       12. The apparatus of  claim 11 , wherein said semiconductor device is based on a slice. 
     
     
       13. The apparatus of  claim 11 , wherein said multiplexer has two input ports. 
     
     
       14. The apparatus of  claim 11 , wherein said multiplexer has at least three input ports. 
     
     
       15. The apparatus of  claim 11 , wherein said reusable field programmable device is a field programmable gate array. 
     
     
       16. The apparatus of  claim 11 , wherein said reusable field programmable device is a programmable logic device.