Method for fabricating semiconductor device by forming damascene interconnections

Abstract

A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, and the first contact holes and the recesses are concurrently filled with a conductive material. The recesses can be filled with the conductive material by performing an etch-back process. The dielectric layer patterns are then etched, thereby forming the damascene interconnections and concurrently covering only a region in which second contact holes are to be formed with the dielectric layer patterns. Spaces between the dielectric layer patterns are filled with a mask layer, and then the dielectric layer patterns are selectively removed from the resultant structure, thereby forming the second contact holes aligned with the damascene interconnections.

1. A method for fabricating a semiconductor device, the method comprising:
 (a) stacking a lower dielectric layer and an upper dielectric layer on a semiconductor substrate; 
 (b) etching the upper dielectric layer, thereby forming dielectric layer patterns that define damascene recesses, wherein an upper portion and a lower portion of each dielectric layer pattern has a first width; 
 (c) etching the lower dielectric layer between the dielectric layer patterns to form first contact holes and etching the upper portion of each dielectric layer pattern to define a first upper portion and a second upper portion, wherein the first upper portions of the dielectric layer patterns have a second width and wherein the second upper portions of the dielectric layer patterns have the first width, wherein the second width is less than the first width; 
 (d) filling the first contact holes with a first conductive material to form first contact plugs, filling the damascene recesses between the lower portions of the dielectric layer patterns with the first conductive material to form damascene interconnections on the first contact plugs and etching the first and second upper portions of the dielectric layer patterns so that only a portion of the second upper portions of each dielectric layer patterns protrudes above the damascene interconnections; 
 (e) covering the damascene interconnections with a mask layer and planarizing the mask layer until the top surface of the dielectric layer patterns remaining after (d) are exposed; 
 (f) selectively removing the exposed dielectric layer patterns and the lower dielectric layer under the exposed dielectric layer patterns to form second contact holes; and 
 (g) filling the second contact holes with a second conductive material to form second contact plugs therein. 
 
   
   
     2. The method of  claim 1 , wherein (d) comprises:
 depositing the first conductive material to fill the first contact holes and spaces between the dielectric layer patterns; and 
 forming the damascene interconnections by planarizing the first conductive material from the top surface of the dielectric layer patterns and performing an etch-back process on the resultant structure so that only a portion of the second upper portion of each dielectric layer pattern protrudes above the damascene interconnections. 
 
   
   
     3. The method of  claim 1 , wherein (d) comprises:
 depositing the first conductive material to fill the first contact holes and spaces between the dielectric layer patterns; 
 forming the damascene interconnections by recessing the first conductive material below the top surface of the dielectric layer patterns and performing an etch-back process so that the overall width of the dielectric layer patterns protruding above the damascene interconnections is reduced; and 
 etching the dielectric layer patterns having the reduced overall width so that only a portion of the second upper portion of each dielectric layer pattern protrudes above the damascene interconnections. 
 
   
   
     4. The method of  claim 3 , wherein etching the dielectric layer patterns having the reduced overall width is performed using dry etching, wet etching, or plasma etching. 
   
   
     5. The method of  claim 1 , wherein the mask layer comprises a material having an etch selectivity with respect to those of the upper dielectric layer and the lower dielectric layer. 
   
   
     6. The method of  claim 1 , wherein the mask layer comprises a nitride layer or an oxynitride layer, and the upper dielectric layer and the lower dielectric layer comprises an oxide layer. 
   
   
     7. The method of  claim 1 , further comprising forming an etch stopper between the lower dielectric layer and the upper dielectric layer. 
   
   
     8. The method of  claim 1 , wherein planarizing the mask layer is performed using an etch-back or a chemical mechanical polishing (CMP) process.