Semiconductor device and method of fabricating the same

Abstract

A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergrate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

1. A method of fabricating a semiconductor device, comprising:
 preparing a substrate including a first area where a logic transistor is to be formed and a second area where a non-volatile memory cell is to be formed; 
 forming a non-volatile memory cell at the second area of the substrate, comprising forming a floating gate on the second area of the substrate, forming an integrate dielectric on the floating gate, forming a control gate on the intergate dielectric and which has a smaller surface area than each of the floating gate and the intergate dielectric such that an upper part of the intergate dielectric is exposed, and forming an insulation layer as an uppermost portion of the non-volatile memory cell and in contact with the upper part of the intergate dielectric exposed by the control gate to thereby enhance the charge retention capability of the memory cell; and 
 forming a logic transistor at the first area of the substrate, comprising selectively forming a silicide layer at the first area. 
 
   
   
     2. The method as recited in  claim 1 , wherein said forming of the insulation layer comprises forming a layer comprising an oxide as the uppermost portion of the non-volatile memory cell. 
   
   
     3. The method as recited in  claim 1 , wherein said forming of the insulation layer comprises forming a layer comprising silicon oxynitride as the uppermost portion of the non-volatile memory cell. 
   
   
     4. The method as recited in  claim 1 , wherein said forming of the insulation layer comprises forming a multi-layered film comprising an oxide and a nitride as the uppermost portion of the non-volatile memory cell. 
   
   
     5. The method as recited in  claim 1 , wherein said forming of the insulation layer comprises forming a multi-layered film selected from the group consisting of an oxide-silicon oxynitride-silicon nitride film, a silicon-silicon oxynitride-oxide film, an oxide-silicon nitride-silicon oxynitride-silicon nitride film, and an oxide-silicon nitride-oxide film as the uppermost portion of the non-volatile memory cell. 
   
   
     6. The method as recited in  claim 5 , wherein said forming a non-volatile memory cell at the second area of the substrate and said forming a logic transistor at the first area of the substrate comprise:
 forming a gate insulation layer on the first and second areas of the substrate, forming a first gate pattern and an intergate dielectric pattern on the gate insulation layer to thereby form the floating gate and the intergate dielectric at the second area of the substrate, and subsequently forming a second gate pattern on the gate insulation layer to thereby form a logic gate at said first area and the control gate on the intergate dielectric, and 
 forming the silicide layer on the logic gate and on the first area of the substrate adjacent opposite sides of the logic gate. 
 
   
   
     7. The method as recited in  claim 6 , wherein said forming of the insulation layer comprises forming the insulation layer over the second area of the substrate including over the control gate before the silicide layer is formed on the first area of the substrate. 
   
   
     8. The method as recited in  claim 6 , wherein said forming of the second gate pattern comprises forming a second gate layer on the substrate, and subsequently patterning the second gate layer to leave on the integrate dielectric a portion of the gate layer having a smaller surface area than each of the floating gate and the integrate dielectric. 
   
   
     9. The method as recited in  claim 1 , wherein:
 said preparing a substrate comprises preparing the substrate to further include a third area where an input/output transistor (I/O) transistor is to be formed, and 
 further comprising forming, at the third area of the substrate, an I/O transistor in which the insulation layer is an uppermost portion thereof. 
 
   
   
     10. The method as recited in  claim 9 , wherein said forming the logic transistor, the I/O transistor, and the non-volatile memory cell at the first, second, and third areas of the substrate comprise:
 forming a gate insulation layer on the first, second, and third areas of the substrate, forming a first gate pattern and an intergate dielectric pattern on the gate insulation layer to thereby form the floating gate and the intergate dielectric at the second area of the substrate, and subsequently forming a second gate pattern on the gate insulation layer to thereby form a logic gate at said first area, the control gate on the intergate dielectric, and an I/O gate at said third area. 
 
   
   
     11. The method as recited in  claim 10 , wherein said forming of the insulation layer comprises forming a layer comprising an oxide as the uppermost portions of the non-volatile memory cell and I/O transistor. 
   
   
     12. The method as recited in  claim 10 , wherein said forming of the insulation layer comprises forming a layer comprising silicon oxynitride as the uppermost portions of the non-volatile memory cell and I/O transistor. 
   
   
     13. The method as recited in  claim 10 , wherein said forming of the insulation layer comprises forming a multi-layered film comprising an oxide and a nitride as the uppermost portions of the non-volatile memory cell and I/O transistor. 
   
   
     14. The method as recited in  claim 10 , wherein said forming of the insulation layer comprises forming a multi-layered film selected from the group consisting of an oxide-silicon oxynitride-silicon nitride film, a silicon-silicon oxynitride-oxide film, an oxide-silicon nitride-silicon oxynitride-silicon nitride film, and an oxide-silicon nitride-oxide film as the uppermost portions of the non-volatile memory cell and I/O transistor. 
   
   
     15. The method as recited in  claim 10 , wherein said forming of the insulation layer comprises forming the insulation layer over the second and third areas of the substrate including over the control gate before the silicide layer is formed on the first area of the substrate. 
   
   
     16. A method of fabricating a semiconductor device, comprising:
 preparing a substrate including a first area where a logic transistor is to be formed, a second area where a non-volatile memory cell is to be formed, and a third area where an input/output transistor (I/O transistor) is to be formed; 
 forming a gate insulation layer on the first, second, and third areas of the substrate; 
 forming a first gate pattern and an intergate dielectric pattern on the gate insulation layer to thereby form a first gate and an intergate dielectric on the second area of the substrate; 
 forming a respective gate on the gate insulation layer at the first area of the substrate, on the intergate dielectric pattern, and on the gate insulation layer at the third area of the substrate, such that the respective gate formed on intergate dielectric pattern has a smaller surface area than each of the first gate and the intergate dielectric so as to expose an upper part of the intergate dielectric; 
 forming an insulation layer over the respective gates formed at the second and third areas of the substrate and in contact with the upper part of the intergate dielectric exposed by the respective gate formed thereon, whereby a non-volatile cell is formed at the second area of the substrate, the insulation layer constituting an uppermost portion of the non-volatile memory cell; and 
 selectively forming a silicide layer on the respective gate formed at the first area of the substrate and on the substrate adjacent opposite sides of the gate formed at the first area. 
 
   
   
     17. The method as recited in  claim 16 , wherein said forming of the insulation layer comprises forming a multi-layered film selected from the group consisting of an oxide-silicon oxynitride-silicon nitride film, a silicon-silicon oxynitride-oxide film, an oxide-silicon nitride-silicon oxynitride-silicon nitride film, and an oxide-silicon nitride-oxide film as the uppermost portion of the non-volatile memory cell. 
   
   
     18. The method as recited in  claim 16 , and further comprising forming insulation spacers on sidewalls of the respective gates formed at the first area of the substrate, on the intergate dielectric pattern, and at the third area of the substrate and on sidewalls of the first gate, all before the insulation layer is formed. 
   
   
     19. The method as recited in  claim 16 , wherein said forming of the respective gate comprises forming a second gate layer on the substrate, and subsequently patterning the second gate layer to leave on the intergate dielectric a portion of the second gate layer having a smaller surface area than each of the first gate on the second area of the substrate and the intergate dielectric.