Locking display pixel clock to input frame rate

Abstract

To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.

1. An integrated circuit comprising:
 a first block configured to determine a period of an input clock signal using a reference clock signal; 
 a second block configured to receive the determined period and to generate a multiplier signal carrying a multiplier value; and 
 a third block configured to multiply the reference clock signal frequency by the multiplier signal to generate a output clock signal, said third block further configured to lock the output clock signal to the reference clock signal, wherein said input clock signal is used for vertical synchronization of input frames. 
 
   
   
     2. The integrated circuit of  claim 1  further comprising:
 a fourth block configured to remove jitter from the multiplier signal. 
 
   
   
     3. The integrated circuit of  claim 2  further comprising:
 a fifth block configured to limit frequency range of signal generated by the fourth block. 
 
   
   
     4. The integrated circuit of  claim 1  wherein said first block is a counter configured to receive the reference clock signal at its clock input terminal, and the input clock signal at its reset terminal. 
   
   
     5. The integrated circuit of  claim 4  wherein said second block is a multiplier block configured to receive the clock input signal at its load terminal, and to receive signals carrying information regarding display frame's height display_height and width display_width, wherein said multiplier block is further configured to generate a multiplier freq_mul as defined below:
   freq_mul= n *(display_width*display_height)/Refclk_cnt, 
 wherein Refclk_cnt represents the period of the input clock signal determined by the counter and n is an integer greater than or equal to 1. 
 
   
   
     6. The integrated circuit of  claim 5  wherein said third block is a fractional-N phase-locked loop block. 
   
   
     7. The integrated circuit of  claim 5  wherein said fractional-N phase-locked loop comprises a delta-sigma modulator. 
   
   
     8. The integrated circuit of  claim 2  wherein said fourth block is an averaging filter. 
   
   
     9. A method of locking an output clock signal to an input clock signal, the method comprising:
 determining a period of the input clock signal using a reference clock signal; 
 generating a multiplier signal carrying a multiplier value using the determined period; 
 multiplying the reference clock signal frequency by the multiplier signal to generate the output clock signal; and 
 locking the output clock signal to the reference clock signal, wherein said input clock signal is used for vertical synchronization of input frames. 
 
   
   
     10. The method of  claim 9  further comprising:
 removing jitter from the multiplier signal to generate an intermediate signal. 
 
   
   
     11. The method of  claim 10  further comprising:
 limiting frequency range of the intermediate signal. 
 
   
   
     12. The method of  claim 9  wherein said multiplier value freq_mul is generated as defined below:
   freq_mul= n *(display_width*display_height)/Refclk_cnt 
 wherein Refclk_cnt represents the period of the input clock signal, display_height represents the height of the display frame, and display_width represents the width of the display frame, and n is an integer greater than or equal to 1.