Fast-locking digital phase locked loop

Abstract

A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

1. A method of synchronizing signals in a device comprising:
 measuring a period of a reference signal having a reference frequency and a reference phase; 
 generating an adjusted reference signal having a frequency approximately equal to the reference frequency, wherein the adjusted reference signal is generated internal to the device; 
 delivering the adjusted reference signal to an oscillator, wherein delivering comprises delivering the adjusted reference signal to a digitally controlled oscillator (DCO) through a feedback loop; 
 locking a frequency of an output signal of the synchronization device with the frequency of the reference signal; and 
 locking a phase of the output signal of the synchronization device with the phase of the reference signal. 
 
     
     
       2. The method, as set forth in  claim 1 , wherein measuring comprises measuring the period of a clock signal. 
     
     
       3. The method, as set forth in  claim 1 , wherein measuring comprises measuring the period using a delay line. 
     
     
       4. The method, as set forth in  claim 1 , wherein generating comprises generating an internal reference signal using a measure controlled delay (MCD) device. 
     
     
       5. The method, as set forth in  claim 1 , wherein generating comprises generating an internal reference signal using a synchronous mirror delay (SMD) device. 
     
     
       6. The method, as set forth in  claim 1 , wherein generating comprises storing the measured period and setting a delay line to a delay equal to one half of the measured period. 
     
     
       7. The method, as set forth in  claim 1 , wherein delivering comprises delivering the adjusted reference signal to the oscillator such that the oscillator begins oscillating at approximately the reference frequency. 
     
     
       8. The method, as set forth in  claim 1 , wherein locking the frequency and the phase of the output signal with the frequency and phase of the reference signal comprises implementing a phase detector. 
     
     
       9. A method of synchronizing signals in a device comprising:
 measuring a period of a reference signal having a reference frequency and a reference phase; 
 generating an adjusted reference signal having a frequency approximately equal to the reference frequency, wherein the adjusted reference signal is generated internal to the device; 
 delivering the adjusted reference signal to an oscillator; 
 locking a frequency of an output signal of the synchronization device with the frequency of the reference signal; and 
 locking a phase of the output signal of the synchronization device with the phase of the reference signal, 
 wherein measuring and generating are performed in two periods. 
 
     
     
       10. A method comprising:
 delivering a reference signal to a first delay line, wherein the reference signal comprises a reference period; 
 measuring the reference period in the first delay line; 
 storing the measured reference period; 
 setting a second delay line to approximately equal to the reference period using a control circuit; 
 delivering an adjusted reference signal from the second delay line to the second delay line through a feedback loop; and 
 locking the adjusted reference signal to the reference signal. 
 
     
     
       11. The method, as set forth in  claim 10 , wherein delivering the reference signal comprises delivering a clock signal. 
     
     
       12. The method, as set forth in  claim 10 , wherein delivering the adjusted reference signal comprises delivering the adjusted reference signal to the second delay line such that the second delay line begins oscillating at a frequency approximately equal to the inverse of the reference period. 
     
     
       13. The method, as set forth in  claim 10 , wherein delivering the adjusted reference signal comprises delivering the adjusted reference signal to a digitally controlled delay line. 
     
     
       14. The method, as set forth in  claim 10 , wherein locking comprises implementing a phase detector.