Methods and circuits for dedicating a programmable logic device for use with specific designs

Abstract

Disclosed are methods and circuits that enable PLD vendors to dedicate PLDs for use with one or more specified designs. The PLD is programmed to store an indicator related to a specific design, for example, a hash function of the design, and to compare an indicator calculated within the PLD from an expression of the design (such as a bitstream) with the stored indicator. Only if the comparison matches is the PLD programmed to implement the design.

1. A programmable logic device comprising:
 a. programmable logic having defective portions; 
 b. configuration memory connected via logic control lines to the programmable logic and adapted to control the function of the programmable logic; and 
 c. configuration logic having:
 i. a memory access bus connected to the configuration memory; 
 ii. at least one configuration access port adapted to receive expressions of customer-specific designs; and 
 iii. design verification circuitry adapted to accept at least a given one of the expressions and to reject others of the expressions based on a unique signature of the given expression indicating the given expression can be instantiated into the configuration logic having the defective portions. 
 
 
   
   
     2. The programmable logic device of  claim 1 , further comprising a register adapted to store the unique signature. 
   
   
     3. The programmable logic device of  claim 2 , wherein the design verification circuitry comprises hash logic adapted to compute the unique signature. 
   
   
     4. The programmable logic device of  claim 2 , further comprising a memory adapted to identify the unique signature. 
   
   
     5. The programmable logic device of  claim 4 , wherein the memory is non-volatile. 
   
   
     6. The programmable logic device of  claim 1 , wherein the design verification circuitry can be disabled from accepting the others of the expressions. 
   
   
     7. The programmable logic device of  claim 6 , further comprising a non-volatile memory cell adapted to disable the design verification circuitry. 
   
   
     8. The programmable logic device of  claim 1 , further comprising a decryptor adapted to receive and decrypt an encrypted expression of a customer-specific design to provide a decrypted expression. 
   
   
     9. The programmable logic device of  claim 8 , wherein the design verification circuitry is adapted to identify at least a portion of the decrypted expression. 
   
   
     10. The programmable logic device of  claim 1 , wherein the expressions are configuration bitstreams, and wherein the design verification circuitry accepts bitstreams of at least one allowed length. 
   
   
     11. The programmable logic device of  claim 10 , further comprising memory adapted to store values indicative of the allowed length. 
   
   
     12. The programmable logic device of  claim 10 , wherein there is only one allowed length.