System and method for detecting accesses to non-existing hardware entities using architectural simulation

Abstract

A system and method for detecting accesses to non-existing hardware entities using a simulator environment. When an application running on a simulated target platform issues a transaction that involves accessing a hardware address, wherein the address is within a range of addresses allocated to a simulated hardware block, a set of instructions provided with the simulator are operable to determine if there exists a backing that corresponds to the transaction's address. If there is no backing (i.e., a control status register) associated with the address, an appropriate notification or warning is provided as a response.

1. A system for detecting accesses to non-existing hardware entities comprising:
 means for examining an address associated with a transaction issued by an application running on a target computer platform that is simulated by an architectural simulator rendered on a host, wherein said transaction's address is within a range of addresses allocated to a simulated hardware block that forms a portion of said target computer platform; and 
 means for initiating an action in response to determining that a control status register corresponding to said transaction's address is absent in said simulated hardware block. 
 
     
     
       2. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said means for initiating an action comprises means for notifying said application that said transaction involves accessing a non-existent hardware entity. 
     
     
       3. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said means for initiating an action comprises means for terminating said architectural simulator. 
     
     
       4. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said means for initiating an action comprises means for providing an alarm to a user. 
     
     
       5. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said target computer platform comprises a multiprocessor computer system selected from at least one of a symmetrical multiprocessor system, an asymmetrical multiprocessor system, a loosely-coupled multiprocessor system and a tightly-coupled multiprocessor system. 
     
     
       6. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said control status register is associated with a simulated processor block. 
     
     
       7. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said control status register is associated with a simulated memory block. 
     
     
       8. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said control status register is associated with a simulated cellular partition of said target computer platform. 
     
     
       9. The system for detecting accesses to non-existing hardware entities as recited in  claim 1 , wherein said control status register is associated with a simulated input/output block. 
     
     
       10. A method of detecting accesses to non-existing hardware entities, comprising:
 examining an address associated with a transaction issued by an application running on a target computer platform that is simulated by an architectural simulator rendered on a host, wherein said transaction's address is within a range of addresses allocated to a simulated hardware block that forms a portion of said target computer platform; 
 determining if there exists in said simulated hardware block a control status register corresponding to said transaction's address; and 
 initiating an action in response to determining that said control status register corresponding to said transaction's address is absent in said simulated hardware block. 
 
     
     
       11. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said action comprises notifying said application that said transaction involves accessing a non-existing hardware entity. 
     
     
       12. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said action comprises terminating said architectural simulator. 
     
     
       13. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said action comprises providing a warning to a user. 
     
     
       14. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said transaction is issued by said application on said target computer platform comprising a multiprocessor computer system. 
     
     
       15. The method of detecting accesses to non-existing hardware entities as recited in  claim 14 , wherein said multiprocessor computer system is selected from at least one of a symmetrical multiprocessor system, an asymmetrical multiprocessor system, a loosely-coupled multiprocessor system and a tightly-coupled multiprocessor system. 
     
     
       16. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said control status register is associated with a simulated processor block. 
     
     
       17. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said control status register is associated with a simulated memory block. 
     
     
       18. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said control status register is associated with a simulated cellular partition of said target computer platform. 
     
     
       19. The method of detecting accesses to non-existing hardware entities as recited in  claim 10 , wherein said control status register is associated with a simulated input/output block. 
     
     
       20. An architectural simulator for detecting accesses to non-existing hardware entities, said architectural simulator operating as code executed on a host machine, comprising:
 instructions for examining an address associated with a transaction issued by an application running on a target computer platform that is simulated by said architectural simulator, wherein said transaction's address is within a range of addresses allocated to a simulated hardware block that forms a portion of said target computer platform; 
 instructions for determining if there exists in said simulated hardware block a control status register corresponding to said transaction's address; and 
 instructions for initiating an action in response to determining that said control status register corresponding to said transaction's address is absent in said simulated hardware block. 
 
     
     
       21. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said instructions for initiating an action comprise instructions for notifying said application that said transaction involves accessing a non-existing hardware entity. 
     
     
       22. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said instructions for initiating an action comprise instructions for terminating said application. 
     
     
       23. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said instructions for initiating an action comprise instructions for providing a warning to a user. 
     
     
       24. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said transaction is issued by said application on said target computer platform comprising a multiprocessor computer system. 
     
     
       25. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said control status register is associated with a simulated processor block. 
     
     
       26. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said control status register is associated with a simulated memory block. 
     
     
       27. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said control status register is associated with a simulated cellular partition of said target computer platform. 
     
     
       28. The architectural simulator for detecting accesses to non-existing hardware entities as recited in  claim 20 , wherein said control status register is associated with a simulated input/output block. 
     
     
       29. A computer system, comprising: an Operating System (OS) operable to support an architectural simulator, said architectural simulator for simulating a target computer platform having at least one processor;
 instructions associated with said architectural simulator for examining an address related to a transaction that is issued by an application running on said target computer platform, wherein said transaction's address is within a range of addresses allocated to a simulated hardware block that forms a portion of said target computer platform; 
 instructions associated with said architectural simulator for determining if there exists in said simulated hardware block a control status register corresponding to said transaction's address; and 
 instructions associated with said architectural simulator for initiating an action in response to determining that said control status register corresponding to said transaction's address is absent in said simulated hardware block. 
 
     
     
       30. The computer system as recited in  claim 29 , wherein said instructions for initiating an action comprise instructions for notifying said application that said transaction involves accessing a non-existing hardware entity. 
     
     
       31. The computer system as recited in  claim 29 , wherein said instructions for initiating an action comprise instructions for terminating said architectural simulator. 
     
     
       32. The computer system as recited in  claim 29 , wherein said instructions for initiating an action comprise instructions for providing a warning to a user. 
     
     
       33. The computer system as recited in  claim 29 , wherein said control status register is associated with a simulated processor block. 
     
     
       34. The computer system as recited in  claim 29 , wherein said control status register is associated with a simulated memory block. 
     
     
       35. The computer system as recited in  claim 29 , wherein said control status register is associated with a simulated cellular partition of said target computer platform. 
     
     
       36. The computer system as recited in  claim 29 , wherein said control status register is associated with a simulated input/output block.