Dynamic transconductance boosting technique for current mirrors

Abstract

Circuits and methods to increase the transconductance of a current mirror in case of small input currents of the current mirror without affecting the transconductance of said current mirror in case of large input currents have been achieved. Key of the invention is a “bypass” formed by a transistor in series with a resistor, wherein the bypass is in parallel to the input transistor of the current mirror. This bypass is only relevant for very small input currents wherein the resistor can be neglected compared to the impedance of the bypass-transistor and therefore the total transconductance of the current mirror is increased in case of very small input currents. For large input currents the resistor of the bypass effectively blocks the “bypass” path. The invention solves e.g. a problem of amplifiers having any kind of dynamic biasing namely that the input impedance of current mirrors becomes too large for very small input currents.

1. A circuit to increase the transconductance of a current mirror in case of small input currents of the current mirror without affecting the transconductance of said current mirror in case of large input currents is comprising:
 a PMOS current mirror comprising an input transistor and an output transistor, wherein the sources of said both transistors are connected to VDD voltage, the drain of the input transistor is connected to the input of the current mirror, the drain of the output transistor is connected to the output of the current mirror, the gates of said both transistors are interconnected, and the gate and the drain of said input transistor are interconnected; and 
 a bypass of said input transistor of said current mirror comprising a resistor and a PMOS transistor, wherein one terminal of said resistor is connected to VDD voltage, the other terminal of the resistor is connected to the source of said PMOS transistor, the gate of said PMOS transistor is connected to the drain of said PMOS transistor and to the drain of said input transistor of said current mirror. 
 
   
   
     2. The circuit of  claim 1  wherein the size of said PMOS transistor of said bypass is much larger than the size of said input transistor of said current mirror. 
   
   
     3. The circuit of  claim 2  wherein the width of said PMOS transistor of said bypass is six-times larger that the width of said input transistor of said current mirror. 
   
   
     4. The circuit of  claim 1  wherein said resistor has a resistance in the order of magnitude of 50 KOhm. 
   
   
     5. The circuit of  claim 1  wherein the transconductance of said bypass transistor matches the transconductance of said input transistor of said current mirror. 
   
   
     6. A circuit to increase the transconductance of a current mirror in case of small input currents of the current mirror without affecting the transconductance of said current mirror in case of large input currents is comprising:
 an NMOS current mirror comprising an input transistor and an output transistor, wherein the sources of said both transistors are connected to VSS voltage, the drain of the input transistor is connected to the input of the current mirror, the drain of the output transistor is connected to the output of the current mirror, the gates of said both transistors are interconnected, and the gate and the drain of said input transistor are interconnected; and 
 a bypass of said input transistor of said current mirror comprising a resistor and a NMOS transistor, wherein one terminal of said resistor is connected to VSS voltage, the other terminal of the resistor is connected to the source of said NMOS transistor, the gate of said NMOS transistor is connected to the drain of said NMOS transistor and to the drain of said input transistor of said current mirror. 
 
   
   
     7. The circuit of  claim 6  wherein the size of said NMOS transistor of said bypass is much larger than the size of said input transistor of said current mirror. 
   
   
     8. The circuit of  claim 7  wherein the width of said NMOS transistor of said bypass is six-times larger that the width of said input transistor of said current mirror. 
   
   
     9. The circuit of  claim 6  wherein said resistor has a resistance in the order of magnitude of 50 KOhm. 
   
   
     10. The circuit of  claim 6  wherein the transconductance of said bypass transistor matches the transconductance of said input transistor of said current mirror. 
   
   
     11. A method to increase the transconductance of a current mirror in case of small input currents of the current mirror without affecting the transconductance of said current mirror in case of large input currents is comprising:
 provide a current mirror comprising an input and an output transistor and a bypass in parallel to said input transistor; 
 ensure, in case of small input currents of said current mirror, that the input transconductance of the current mirror is increased by the transconductance of said bypass; and 
 ensure, in case of large input currents of said current mirror, that the input transconductance of the current mirror is not impacted by the bypass. 
 
   
   
     12. The method of  claim 11  wherein said bypass comprises a transistor in series with a resistor. 
   
   
     13. The method of  claim 12  wherein said transistor of said bypass and the transistors of said current mirror are PMOS transistors. 
   
   
     14. The method of  claim 13  wherein said PMOS transistor of said bypass is significantly larger than said input transistor of said current mirror. 
   
   
     15. The method of  claim 13  wherein the transconductance of said PMOS transistor of said bypass matches the transconductance of said input transistor of said current mirror. 
   
   
     16. The method of  claim 13  wherein said transistor of said bypass and the transistors of said current mirror are NMOS transistors. 
   
   
     17. The method of  claim 16  wherein said NMOS transistor of said bypass is significantly larger than said input transistor of said current mirror. 
   
   
     18. The method of  claim 16  wherein the transconductance of said NMOS transistor of said bypass matches the transconductance of said input transistor of said current mirror. 
   
   
     19. The method of  claim 13  wherein said transistor of said bypass and the transistors of said current mirror are pnp bipolar transistors. 
   
   
     20. The method of  claim 19  wherein said pnp bipolar transistor of said bypass is significantly larger than said input transistor of said current mirror. 
   
   
     21. The method of  claim 19  wherein the transconductance of said pnp bipolar transistor of said bypass matches the transconductance of said input transistor of said current mirror. 
   
   
     22. The method of  claim 13  wherein said transistor of said bypass and the transistors of said current mirror are npn bipolar transistors. 
   
   
     23. The method of  claim 22  wherein said npn bipolar transistor of said bypass is significantly larger than said input transistor of said current mirror. 
   
   
     24. The method of  claim 23  wherein the transconductance of said NMOS transistor of said bypass matches the transconductance of said input transistor of said current mirror.