SDRAM controller that improves performance for imaging applications

Abstract

A method and apparatus for efficient access to multiple lines of image data using a memory device with at least one memory module, wherein each memory module has at least one bank with multiple rows. The method includes the step of maintaining address information of a current row for each bank within each memory module. Next, the method receives a request for an incoming row. Finally, the method determines if the incoming row matches the current row based on the address information and if so, immediately accesses the current row without closing and reopening the current row.

1. A method for efficient access to multiple lines of image data using a memory device with at least one memory module, wherein each memory module has at least one bank with multiple rows, the method comprising the steps of:
 maintaining address information of a current row for each bank within each memory module; 
 receiving a request for an incoming row; 
 determining if the incoming row matches the current row based on the address information and if so, immediately accessing the current row without closing and reopening the current row; 
 receiving a request for a desired memory format from an external structure; and 
 selecting the desired memory format from different address multiplexing schemes. 
 
   
   
     2. The method according to  claim 1  wherein the step of maintaining address information comprises the steps of:
 setting an open bit when the current row is opened; and clearing the open bit when the current row is closed. 
 
   
   
     3. The method according to  claim 1  further comprising the step of maintaining programmable counters to monitor timing parameters and detect legal and illegal actions. 
   
   
     4. The method according to  claim 1  further comprising the step of positioning adjacent lines of the image data in separate memory banks to optimize access to multiple lines of the image data. 
   
   
     5. The method according to  claim 1  wherein the memory modules are SDRAM modules, each having four banks. 
   
   
     6. A memory controller for efficient access to multiple lines of image data using at least one memory module, wherein each memory module has at least one bank with multiple rows, the memory controller comprising:
 means for maintaining address information of a current row for each bank within each memory module; 
 means for receiving a request for an incoming row; and means for determining if the incoming row matches the current row based on the address information and if so, immediately accessing the current row without closing and reopening the current row; 
 means for receiving a request for a desired memory format from an external structure; and 
 means for selecting the desired memory format from different address multiplexing schemes. 
 
   
   
     7. The memory controller according to  claim 6  wherein the means for maintaining address information comprises:
 means for setting an open bit when the current row is opened; and 
 means for clearing the open bit when the current row is closed. 
 
   
   
     8. The memory controller according to  claim 6  further comprising programmable counters maintained to monitor timing parameters and detect legal and illegal actions. 
   
   
     9. The memory controller according to  claim 6  wherein adjacent lines of the image data are positioned in separate memory banks to optimize access to multiple lines of the image data. 
   
   
     10. The memory controller according to  claim 6  wherein the memory modules are SDRAM modules, each having four banks.