Method for fabricating semiconductor device having first and second gate electrodes

Abstract

A method of fabricating a gate electrode used for more flexible device design and higher device integrity is disclosed. A disclosed method comprises: forming a first gate electrode by etching the first insulating layer and the first polysilicon layer; forming a second insulating layer and a second polysilicon layer on the resulting structure; forming a second gate electrode by etching the second polysilicon layer, wherein the longitudinal axes of the first and second gate electrodes cross each other at a predetermined angle; forming a third insulating layer on the resulting structure; and forming source and drain regions by an ion implantation.

1. A method for fabricating a semiconductor device comprising:
 forming a first insulating layer and a first polysilicon layer on a semiconductor substrate; 
 forming a first gate electrode by etching the first insulating layer and the first polysilicon layer; 
 forming a second insulating layer and a second polysilicon layer on the first gate electrode and semiconductor substrate; 
 forming a second gaze electrode by etching the second polysilicon layer, wherein the longitudinal axes of the first and second gate electrodes cross ouch other at a predetermined angle, and the first and the second gate electrodes provide six source-drain combinations; 
 forming a third insulating layer on the first and second gate electrodes and the semiconductor substrate; and 
 forming source and drain regions by an ion implantation into the semiconductor substrate. 
 
   
   
     2. A method as defined by  claim 1 , wherein the first, second and third insulating layers comprise thermal oxides. 
   
   
     3. A method as defined by  claim 1 , wherein the predetermined angle is about 90°. 
   
   
     4. A method as defined by  claim 1 , wherein the ion implantation forms four source and drain regions. 
   
   
     5. A method as defined by  claim 1 , wherein the source-drain combinations are determined by controlling the first and second gate electrodes. 
   
   
     6. A method as defined by  claim 1 , wherein forming the first gate electrode comprises coating the first polysilicon layer with a photoresist and forming a pattern by exposure and development processes. 
   
   
     7. A method as defined by  claim 1 , wherein the second insulating layer protects or insulates exposed silicon on a sidewall or surface of the first gate electrode. 
   
   
     8. A method as defined by  claim 1 , wherein the second insulating layer has characteristics of a gate insulating layer for the second gate electrode. 
   
   
     9. A method as defined by  claim 1 , wherein the first insulating layer comprises a thermal oxide. 
   
   
     10. A method as defined by  claim 9 , wherein the second insulating layer comprises a thermal oxide. 
   
   
     11. A method as defined by  claim 1 , wherein the second insulating layer comprises a thermal oxide. 
   
   
     12. A method as defined by  claim 11 , wherein the third insulating layer comprises a thermal oxide. 
   
   
     13. A method as defined by  claim 1 , wherein the third insulating layer comprises a thermal oxide. 
   
   
     14. A method as defined by  claim 1 , wherein the ion implantation forms first and second source regions and first and second drain regions.