Method and apparatus for DC offset cancellation

Abstract

A radio transceiver includes amplification circuitry that is coupled to receive a down converted signal and to provide infinite rejection of any DC component added by the down conversion circuitry. Specifically, an amplification stage includes a voltage integrator that is coupled within a feedback loop of the amplification circuitry to produce a DC charge having a magnitude that equals the added DC component but a polarity that is opposite. Accordingly, the voltage produced by the voltage integrator is added to the signal received from the down conversion circuitry to cause the amplification circuitry to merely amplify the wireless communication signals characterized by a frequency of oscillation. Logic circuitry is used for selectively coupling the voltage integrator to an output port of the amplification circuitry.

1. A receiver, comprising:
 an input port for receiving a RF wireless signal; 
 down conversion circuitry coupled to receive the RF signal from the input port and producing a down converted baseband frequency signal; 
 amplification circuitry coupled to receive the down converted baseband frequency signal and any DC signals introduced by the down conversion circuitry, the amplification circuitry for amplifying the received down converted baseband frequency signal; and 
 a voltage integrator for charging a capacitor with a voltage that matches any DC signals introduced by the down conversion circuitry, the voltage integrator coupled to produce a charge having a DC voltage value that is opposite in polarity to the DC signals introduced by the down conversion circuitry to the input of the amplification circuitry; 
 a MOSFET configured to operate as a resistor whenever a bias voltage is applied to a gate of the MOSFET, wherein the MOSFET is coupled between an input port of the voltage integrator and an output port of the amplification circuitry; and 
 logic circuitry coupled to produce the bias voltage to the gate of the MOSFET to selectively charge the capacitor. 
 
   
   
     2. The receiver of  claim 1  wherein the logic circuitry is coupled to receive an indication of a transition event wherein the transition event reflects that the transceiver device is changing to a normal mode of operation from one of an off state or standby mode of operation. 
   
   
     3. The receiver of  claim 2  wherein the logic circuitry provides a bias voltage to the gate of the MOSFET for a period that is approximately equal to or less than a specified settling time for the transceiver device. 
   
   
     4. The receiver of  claim 3  wherein the bias voltage for the gate of the MOSFET is produced to the gate for a period that is approximately equal to or less than 10 microseconds. 
   
   
     5. The receiver of  claim 1  wherein the MOSFET is coupled to a negative input of the voltage integrator and wherein the MOSFET is a p-channel enhancement MOSFET and further wherein the MOSFET is turned off by applying a voltage approximately equal to VDD. 
   
   
     6. The receiver of  claim 1  further including an adder for adding an output produced from the voltage integrator to the wireless signal received at the input port. 
   
   
     7. The receiver of  claim 1  further including baseband processing circuitry for receiving an amplified output of the amplification circuitry and for processing the received amplified output from the amplification circuitry. 
   
   
     8. The receiver of  claim 1  further comprising a mixer for producing a down converted baseband frequency signal including an I component. 
   
   
     9. The receiver of  claim 8  further comprising a mixer for producing a down converted baseband frequency signal including a Q component. 
   
   
     10. The receiver of  claim 9  wherein the amplification circuitry includes a voltage integrator coupled in a feedback loop of the amplification circuitry for removing any DC signals introduced by the down conversion circuitry. 
   
   
     11. The receiver of  claim 10  wherein the voltage integrator serves to build up a DC charge and to pass high frequency signals in a first state of operation. 
   
   
     12. The receiver of  claim 11  wherein the voltage integrator provides the built up DC charge only in a second state of operation to a negative terminal of the amplification circuitry. 
   
   
     13. A receiver, comprising:
 an input port for receiving a RF wireless signal; 
 down conversion circuitry coupled to receive the RF signal from the input port and producing a down converted baseband frequency signal; 
 amplification circuitry coupled to receive the down converted baseband frequency signal and any DC signals introduced by the down conversion circuitry, the amplification circuitry for amplifying the received down converted baseband frequency signal; and 
 a voltage integrator for charging a capacitor with a voltage that matches any DC signals introduced by the down conversion circuitry, the voltage integrator coupled to produce a charge having a DC voltage value that is opposite in polarity to the DC signals introduced by the down conversion circuitry to the input of the amplification circuitry; 
 a MOSFET configured to operate as a resistor whenever a bias voltage is applied to a gate of the MOSFET, wherein the MOSFET is coupled between an input port of the voltage integrator and an output port of the amplification circuitry; and 
 wherein the MOSFET is coupled to a negative input of the voltage integrator and wherein the MOSFET is a p-channel enhancement MOSFET and further wherein the MOSFET is turned off by applying a voltage approximately equal to VDD. 
 
   
   
     14. The receiver of  claim 13  wherein the logic circuitry is coupled to receive an indication of a transition event wherein the transition event reflects that the transceiver device is changing to a normal mode of operation from one of an off state or standby mode of operation. 
   
   
     15. The receiver of  claim 14  wherein the logic circuitry provides a bias voltage to the gate of the MOSFET for a period that is approximately equal to or less than a specified settling time for the transceiver device. 
   
   
     16. The receiver of  claim 15  wherein the bias voltage for the gate of the MOSFET is produced to the gate for a period that is approximately equal to or less than 10 microseconds.