Method of forming a varactor with an increased linear tuning range

Abstract

The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

1. A method of forming a varactor in a first semiconductor region, the first semiconductor region having a first conductivity type and a first dopant concentration, the method comprising:
 forming a layer of isolation material over the first semiconductor region; 
 forming a layer of second semiconductor material on the layer of isolation material; 
 etching the layer of second semiconductor material to form a first gate on the layer of isolation material; 
 forming a first diffusion region in the first semiconductor region to contact the first semiconductor region, the first diffusion region having a second conductivity type and a second dopant concentration; 
 forming a spacer over the first diffusion region to adjoin the first gate; and 
 forming a second diffusion region in the first semiconductor region to contact the first semiconductor region and adjoin the first diffusion region, the second diffusion region being formed after the first diffusion region, and having the first conductivity type and a third dopant concentration that is greater than the first dopant concentration. 
 
   
   
     2. The method of  claim 1  wherein the first semiconductor region has a top surface, the first diffusion region extends from the top surface a first distance vertically below the top surface, the second diffusion region extends from the top surface a second distance vertically below the top surface, the second distance being greater than the first distance. 
   
   
     3. The method of  claim 1  wherein the first semiconductor region is a well formed in a semiconductor material. 
   
   
     4. The method of  claim 1  wherein the first diffusion region lies between a point that contacts the top surface vertically below the first gate and the second diffusion region. 
   
   
     5. The method of  claim 1  wherein the first gate is doped when the first diffusion region is formed. 
   
   
     6. The method of  claim 5  wherein the first gate is doped when the second diffusion region is formed. 
   
   
     7. The method of  claim 1  wherein the first semiconductor region has a top surface, and the first and second diffusion regions both contact the top surface of the first semiconductor region after the second diffusion region has been formed. 
   
   
     8. The method of  claim 7  wherein the second semiconductor material includes polysilicon. 
   
   
     9. The method of  claim 7  wherein:
 when the layer of isolation material is formed, the layer of isolation material is formed over a second semiconductor region, the second semiconductor region being spaced-apart from the first semiconductor region, and having the first conductivity type and the first dopant concentration; 
 when the layer of second semiconductor material is formed, the layer of second semiconductor material is formed on the layer of isolation material over the second semiconductor region; 
 when the layer of second semiconductor material is etched, a second gate is formed on the layer of isolation material over the second semiconductor region; and 
 when the first diffusion region is formed, spaced-apart third diffusion regions are formed in the second semiconductor region, the spaced-apart third diffusion regions have the second conductivity type and the second dopant concentration. 
 
   
   
     10. The method of  claim 9  and further comprising forming spaced-apart fourth diffusion regions in the second semiconductor region to adjoin the spaced-apart third diffusion regions, the spaced-apart fourth diffusion regions having the second conductivity type and a fourth dopant concentration that is greater than the second dopant concentration. 
   
   
     11. The method of  claim 9  wherein the spaced-apart third diffusion regions lie between the spaced-apart fourth diffusion regions. 
   
   
     12. The method of  claim 9  wherein the first and second semiconductor regions are wells formed in a semiconductor material. 
   
   
     13. The method of  claim 9  wherein:
 when the layer of isolation material is formed, the layer of isolation material is formed over a third semiconductor region, the third semiconductor region being spaced-apart from the first and second semiconductor regions, and having the second conductivity type; 
 when the layer of second semiconductor material is formed, the layer of second semiconductor material is formed on the layer of isolation material over the third semiconductor region; 
 when the layer of second semiconductor material is etched, a third gate is formed on the layer of isolation material over the third semiconductor region; and 
 when the second diffusion region is formed, spaced-apart fourth diffusion regions are formed in the third semiconductor region, the spaced-apart fourth diffusion regions have the first conductivity type and the third dopant concentration. 
 
   
   
     14. The method of  claim 9  wherein the first and second gates are doped when the first diffusion region and the spaced-apart third diffusion regions are formed. 
   
   
     15. The method of  claim 14  wherein the first gate is doped when the second diffusion region is formed.