Device isolation for semiconductor devices

Abstract

Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in the semiconductive substrate by being aligned to the first trench; and an insulation material substantially filling the first and second trenches. The isolation structure separates a non-continuous surface of a conductive region.

1. A process for forming device isolation for a semiconductor assembly comprising:
 forming a first trench having sidewalls into a semiconductor substrate; 
 forming a single dielectric layer lining a surface of the first trench; 
 forming spacers of oxidizable material along the sidewalls of the first trench over and in direct contact with the single dielectric layer; 
 forming a second trench into the semiconductor substrate at the bottom of the first trench using the spacers as an etching guide, wherein an overall depth of the first and second trenches is two times a depth of a bordering diffusion region determined by an area containing at least 90% concentration of conductive atoms; 
 forming an insulative material in the first and second trenches at least partially by substantially consuming the oxidizable material of the spacers. 
 
   
   
     2. The process as recited in  claim 1 , wherein forming the insulative material comprises annealing the semiconductor assembly in the presence of an oxidizing agent. 
   
   
     3. The process as recited in  claim 1 , wherein said process uses only one mask to form the device isolation. 
   
   
     4. A process for forming device isolation for a semiconductor assembly comprising:
 forming a first trench having sidewalls into a semiconductor substrate; 
 forming a single dielectric layer lining a surface of the first trench; 
 forming dielectric spacers along the sidewalls of the first trench over and in direct contact with the single dielectric layer; 
 forming a second trench into the semiconductor substrate at the bottom of the first trench using the spacers as an etching guide, wherein an overall depth of the first and second trenches is two times a depth of a bordering diffusion region determined by an area containing at least 90% concentration of conductive atoms; 
 forming a semiconductive material layer that overlies the dielectric spacers and lines the second trench; and 
 forming an insulative material in the first and second trenches at least partially by substantially consuming the dielectric spacers and the semiconductive material layer. 
 
   
   
     5. The process as recited in  claim 4 , wherein forming the insulative material comprises annealing the semiconductor assembly in the presence of an oxidizing agent. 
   
   
     6. The process as recited in  claim 4 , wherein the process uses only one mask to form the device isolation. 
   
   
     7. A process for forming device isolation for a semiconductor assembly comprising:
 forming a first trench having sidewalls into a semiconductor substrate; 
 forming a single nitride layer lining a surface of the first trench; 
 forming oxide spacers along the sidewalls of the first trench over and in direct contact with the single nitride layer; 
 forming a second trench into the semiconductor substrate at the bottom of the first trench using the spacers as an etching guide, wherein an overall depth of the first and second trenches is two times a depth of a bordering diffusion region determined by an area containing at least 90% concentration of conductive atoms; 
 forming a semiconductive material layer that overlies the oxide spacers and lines the second trench; 
 forming an oxide filler in the first and second trenches at least partially by substantially consuming the oxide spacers and the semiconductive material layer; and 
 planarizing the oxide filler. 
 
   
   
     8. The process as recited in  claim 7 , wherein forming the oxide filler comprises
 annealing the semiconductor assembly in the presence of an oxidizing agent. 
 
   
   
     9. The process as recited in  claim 7 , wherein the process uses only one mask to form the device isolation.