Process for forming a buried plate

Abstract

A method of making a buried plate region in a semiconductor substrate is provided. A trench is formed in a semiconductor substrate, the trench having a trench sidewall, the sidewall including an upper portion, and a lower portion disposed below the upper portion. A liner is formed along at least a portion of the trench sidewall, and thereafter, a dopant source layer is formed over the liner along the lower portion of the trench sidewall. The semiconductor substrate is then annealed to drive a dopant into the semiconductor substrate adjacent to the lower portion of the trench sidewall, while preventing the dopant from being driven into the semiconductor substrate adjacent to the upper portion of the trench sidewall.

1. A method of making a buried plate region in a semiconductor substrate, comprising:
 forming a trench in a semiconductor substrate, the trench having a trench sidewall, the trench sidewall including an upper portion, and a lower portion disposed below the upper portion; 
 forming a liner along at least the lower portion of the trench sidewall; 
 thereafter forming a dopant source layer overlying the liner, the dopant source layer not being disposed along the upper portion of the trench sidewall; and 
 annealing the semiconductor substrate to drive a dopant from the dopant source layer through the liner into the semiconductor substrate adjacent to the lower portion of the trench sidewall while preventing the dopant from being driven into the semiconductor substrate adjacent to the upper portion of the trench sidewall, 
 wherein the liner functions as a diffusion barrier inhibiting diffusion of at least one of oxygen or the dopant into the semiconductor substrate during the step of forming the dopant source layer, and permits the dopant to diffuse through the liner into the semiconductor substrate during the step of annealing to form the buried plate. 
 
   
   
     2. A method as claimed in  claim 1 , wherein a cap layer is formed in the trench to prevent the dopant from being driven into the semiconductor substrate adjacent to the upper portion. 
   
   
     3. A method as claimed in  claim 1 , wherein the liner is formed by thermal nitridation. 
   
   
     4. A method as claimed in  claim 3 , wherein the liner has a thickness of between about 7 Å and 10 Å. 
   
   
     5. A method as claimed in  claim 1 , wherein the liner is formed by thermal oxidation. 
   
   
     6. A method as claimed in  claim 3 , wherein the liner has a thickness of about 20 Å. 
   
   
     7. A method as claimed in  claim 1 , wherein the cap layer consists essentially of an oxide. 
   
   
     8. A method as claimed in  claim 1 , wherein the cap layer consists essentially of an undoped oxide. 
   
   
     9. A method as claimed in  claim 1 , wherein the cap layer is a nitride layer. 
   
   
     10. A method as claimed in  claim 1 , wherein the annealing is conducted at a temperature of above about 900° C. 
   
   
     11. A method as claimed in  claim 1 , wherein the annealing is conducted at a temperature of about 1050° C. 
   
   
     12. A method as claimed in  claim 1 , further comprising removing the cap layer, the dopant source layer and the liner from the trench sidewall after the annealing, and thereafter etching material of the substrate exposed at the trench sidewall selectively to lightly doped semiconductor material, whereby the more heavily doped semiconductor material present at the lower portion of the trench sidewall is etched more rapidly than the more lightly doped semiconductor material present at the upper portion to widen the trench along the lower portion. 
   
   
     13. A method as claimed in  claim 1 , further comprising removing the cap layer, the dopant source layer and the liner from the trench sidewall after the annealing, thereafter forming a collar along the upper portion of the trench sidewall, and then widening the lower portion of the trench sidewall. 
   
   
     14. A method as claimed in  claim 1 , wherein the dopant source layer is formed by depositing arsenic doped glass (ASG) at a temperature of about 700° C. 
   
   
     15. A method of making a trench capacitor having a buried plate formed according to a method as claimed in  claim 1 , further comprising:
 forming a node dielectric along the lower portion of the trench sidewall after removing the liner and the dopant source layer; and 
 depositing at least one of a conductive and a semiconducting material onto the node dielectric as a second plate opposing the buried plate. 
 
   
   
     16. The method of  claim 1  wherein the liner and the dopant source layer are formed in the lower portion of the trench sidewall by forming the liner, forming the dopant source layer over the liner, depositing a cover material over the dopant source layer, recessing the cover material to a predetermined level, and removing the liner and the dopant source layer from the upper portion of the trench sidewall. 
   
   
     17. A method of forming a trench in a semiconductor substrate and a buried plate in the semiconductor substrate adjacent to a lower portion of the trench sidewall, comprising:
 forming a pad stack on a semiconductor substrate and patterning the pad stack to form an opening; 
 patterning a trench having a trench sidewall through the opening by vertically etching the semiconductor substrate selective to a material of the pad stack; 
 forming a liner substrate along the trench sidewall; 
 forming a dopant source layer overlying the liner along lower portion of the trench sidewall; 
 forming a cap layer covering at least an upper portion of the trench sidewall above the lower portion; and 
 annealing to drive a dopant from the dopant source layer through the liner into the semiconductor substrate adjacent to the lower portion to form a buried plate, 
 wherein the liner functions as a diffusion barrier inhibiting diffusion of at least one of oxygen or the dopant into the semiconductor substrate during the step of forming the dopant source layer, and permits the dopant to diffuse through the liner into the semiconductor substrate during the step of annealing to form the buried plate. 
 
   
   
     18. A method as claimed in  claim 17 , wherein the dopant source layer includes arsenic doped glass, the liner is formed by at least one of thermal oxidation and thermal nitridation, and the cap layer consists essentially of an undoped oxide. 
   
   
     19. A method of forming a trench capacitor in a semiconductor substrate, comprising:
 forming a pad stack on a semiconductor substrate and patterning the pad stack to form an opening; 
 patterning a trench having a trench sidewall through the opening by vertically etching the substrate selective to a material of the pad stack; 
 forming a liner on the semiconductor substrate along a sidewall of the trench sidewall; 
 forming a dopant source layer overlying the liner; 
 removing the dopant source layer from the liner along an upper portion of the trench sidewall, while allowing the dopant source layer to remain along a lower portion of the trench sidewall disposed below the upper portion; 
 forming a cap layer covering at least the upper portion of the trench sidewall; 
 annealing to drive a dopant from the dopant source layer through the liner into the semiconductor substrate adjacent to the lower portion to form a buried plate; 
 removing the cap layer, the dopant source layer and the liner from at least the lower portion of the trench sidewall; 
 forming a node dielectric along the lower portion of the trench sidewall; and 
 forming a node electrode on a side of the node dielectric opposite the buried plate, 
 wherein the liner functions as a diffusion barrier inhibiting diffusion of at least one of oxygen or the dopant into the semiconductor substrate during the step of forming the dopant source layer, and permits the dopant to diffuse through the liner into the semiconductor substrate during the step of annealing to form the buried plate. 
 
   
   
     20. A method as claimed in  claim 19 , wherein the liner is formed by at least one of thermal oxidation and thermal nitridation, the dopant source layer includes arsenic doped glass (ASG), and the cap layer consists essentially of an undoped oxide, the method further comprising widening the lower portion prior to forming the node dielectric and prior to forming the node electrode.