Magnetic random access memory

Abstract

In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

1. A magnetic random access memory comprising:
 memory cells which are connected in parallel with each other and use a magnetoresistive effect; 
 a first data transfer line which is connected to one terminal of each of said memory cells and extends in a first direction; 
 a second data transfer line which is connected to the other terminal of each of said memory cells and extends in the first direction; 
 first and second write bit line drivers/sinkers which supply a write current to said first data transfer line or absorb the write current from said first data transfer line; 
 a first switch connected between one end of said first data transfer line and said first write bit line driver/sinker; 
 a second switch connected between the other end of said first data transfer line and said second write bit line driver/sinker; 
 a read circuit which supplies a read current to said first and second data transfer lines; and 
 write word lines extending in a second direction perpendicular to the first direction. 
 
   
   
     2. A memory according to  claim 1 , wherein said second data transfer line is directly connected to a ground terminal. 
   
   
     3. A memory according to  claim 1 , further comprising:
 a third switch connected between said second data transfer line and a ground terminal; and 
 a read word line which is connected to a control terminal of said third switch and extends in the second direction. 
 
   
   
     4. A memory according to  claim 3 , wherein a column of a memory cell array is constituted by blocks, and each of said blocks is constituted by said memory cells. 
   
   
     5. A memory according to  claim 1 , wherein said first and second switches are turned on in write operation and read operation. 
   
   
     6. A memory according to  claim 3 , wherein said third switch is turned on in read operation.