US7022913B2ExpiredUtilityA1

Electronic component, method of manufacturing the electronic component, and electronic apparatus

Assignee: SEIKO EPSON CORPPriority: Jan 9, 2004Filed: Dec 20, 2004Granted: Apr 4, 2006
Est. expiryJan 9, 2024(expired)· nominal 20-yr term from priority
H10W 90/722H10W 90/297H10W 90/20H10W 72/9415H10W 72/9226H10W 72/942H10W 72/923H10W 72/922H10W 72/252H10W 72/251H10W 70/65H10W 90/00H10W 72/20H10W 20/20H10W 72/9445H10W 70/656H10W 74/129H10W 72/90
40
PatentIndex Score
0
Cited by
9
References
20
Claims

Abstract

An electronic component includes a substrate; a functional part that is formed beneath at least one of a front face and a bottom face of the substrate and that performs a predetermined function; a plurality of terminals that is formed on the front face or the bottom face of the substrate and that is connected to the functional part; a plurality of outer electrodes formed on the front face and the bottom face of the substrate; and interconnection lines, formed on the front face and the bottom face of the substrate, for connecting the terminals on the front face or the bottom face of the substrate to the outer electrodes.

Claims

exact text as granted — not AI-modified
1. An electronic component comprising:
 a substrate; 
 a functional part that is formed beneath at least one of a front face and a bottom face of the substrate and that performs a predetermined function; 
 a plurality of terminals that is formed on the front face or the bottom face of the substrate and that is connected to the functional part; 
 a plurality of outer electrodes formed on the front face and the bottom face of the substrate; and 
 interconnection lines, formed on the front face and the bottom face of the substrate, for connecting the terminals on the front face or the bottom face of the substrate to the outer electrodes. 
 
     
     
       2. The electronic component according to  claim 1 ,
 wherein the distance between two adjacent outer electrodes among the plurality of outer electrodes is larger than the distance between two adjacent terminals among the plurality of terminals. 
 
     
     
       3. The electronic component according to  claim 1 , further comprising stress relief layers formed on the front face and the bottom face of the substrate,
 wherein the outer electrodes and the interconnection lines are formed on the stress relief layers. 
 
     
     
       4. The electronic component according to  claim 1 ,
 wherein the plurality of outer electrodes on the front face of the substrate are plane symmetric with the plurality of outer electrodes on the bottom face of the substrate, 
 wherein the outer electrodes connected to the same terminal is provided on both the front face of the substrate and the bottom face thereof, and 
 wherein the outer electrodes connected to the same terminal are line symmetric with each other, on both the front face of the substrate and the bottom face thereof. 
 
     
     
       5. The electronic component according to  claim 1 ,
 wherein the plurality of outer electrodes on the front face of the substrate are plane symmetric with the plurality of outer electrodes on the bottom face of the substrate, 
 wherein the outer electrodes connected to the same terminal is provided on both the front face of the substrate and the bottom face thereof, and 
 wherein the outer electrodes connected to the same terminal are point symmetric with each other, on both the front face of the substrate and the bottom face thereof. 
 
     
     
       6. The electronic component according to  claim 1 ,
 wherein the terminals are formed on the front face or the bottom face of the substrate through corresponding through-holes or plugs extending through the substrate. 
 
     
     
       7. The electronic component according to  claim 6 ,
 wherein the through-holes or plugs are formed immediately below the corresponding terminals. 
 
     
     
       8. The electronic component according to  claim 1 ,
 wherein the outer electrodes connected to the same terminal are subjected to the same surface finishing. 
 
     
     
       9. The electronic component according to  claim 8 ,
 wherein the surface of each of the outer electrodes is subjected to the surface finishing using gold or solder. 
 
     
     
       10. The electronic component according to  claim 1 ,
 wherein the substrate is square. 
 
     
     
       11. The electronic component according to  claim 1 ,
 wherein the width and depth of the electronic component is larger than the thickness thereof. 
 
     
     
       12. The electronic component according to  claim 1 ,
 wherein the substrate is a semiconductor substrate, and 
 wherein the functional part includes at least one active element formed on the semiconductor substrate. 
 
     
     
       13. The electronic component according to  claim 1 ,
 wherein the functional part includes a semiconductor device mounted on the substrate. 
 
     
     
       14. A multilayer electronic component having the electronic components according to  claim 1  arbitrarily combined with each other and layered through the outer electrodes. 
     
     
       15. A multilayer electronic component having the electronic components according to  claim 1  and other components layered through the outer electrodes. 
     
     
       16. An electronic apparatus having the electronic component according to  claim 1  mounted. 
     
     
       17. A method of manufacturing an electronic component, the method comprising steps of:
 forming a functional part, performing a predetermined function, beneath at least one of a front face and a bottom face of a substrate; 
 leading a plurality of terminals from one face of the two faces to the other faces thereof, the terminals being connected to the functional part and extending through the substrate; and 
 forming a plurality of outer electrodes on the front face and the bottom face of the substrate to connect the outer electrodes to the corresponding terminals. 
 
     
     
       18. The method of manufacturing the electronic component according to  claim 17 ,
 wherein, in the step of forming the plurality of outer electrodes, the plurality of outer electrodes on the front face of the substrate are plane symmetric with the plurality of outer electrodes on the bottom face of the substrate, and 
 wherein the outer electrodes connected to the same terminal are line symmetric with each other, on both the front face of the substrate and the bottom face thereof. 
 
     
     
       19. The method of manufacturing the electronic component according to  claim 17 ,
 wherein, in the step of forming the plurality of outer electrodes, the plurality of outer electrodes on the front face of the substrate are plane symmetric with the plurality of outer electrodes on the bottom face of the substrate, and 
 wherein the outer electrodes connected to the same terminal are point symmetric with each other, on both the front face of the substrate and the bottom face thereof. 
 
     
     
       20. The method of manufacturing the electronic component according to  claim 17 ,
 wherein the step of forming the plurality of outer electrodes is performed on stress relief layers after the stress relief layers are formed on the front face and the bottom face of the substrate.

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