Universal serial bus circuit and data structure

Abstract

A USB circuit that can prevent phase difference between a signal pair with high precision without the need for strict design conditions. In a preferred embodiment of this USB circuit, the USB controller thereof comprises a flip-flop pair to match the timings of a signal pair output to an output signal line pair and a flip-flop pair to match the timings of a signal pair input from an input signal line pair, and the USB driver thereof comprises a third flip-flop pair to match the timings of a signal pair input from the output signal line pair, and a fourth flip-flop pair to match the timings of a signal pair output to the input signal line pair.

1. A universal serial bus circuit comprising:
 a universal serial bus controller formed on a semiconductor chip; 
 a universal serial bus driver formed on said semiconductor chip; 
 a first signal line pair and a second signal line pair formed on said semiconductor chip for connecting said universal serial bus controller and said universal serial bus driver; 
 a first flip-flop pair provided in said universal serial bus controller which makes a timing of a first signal pair output to said first signal line pair, by latching the first signal pair at substantially the same time; 
 a second flip-flop pair provided in the universal serial bus controller which makes a timing of a second signal pair input from said second signal line pair, by latching the second signal pair at substantially the same time; 
 a third flip-flop pair provided in the universal serial bus driver which matches the timing of said first signal pair input from said first signal line pair, by latching the first signal pair at substantially the same time; and 
 a fourth flip-flop pair provided in the universal serial bus driver which matches the timing of said second signal pair output to said second signal line pair, by latching the second signal pair at substantially the same time. 
 
   
   
     2. The universal serial bus circuit according to  claim 1 , wherein an operating clock is supplied to said second and third flip-flop pairs and the operating clock is supplied to said first and fourth flip-flop pairs after a prescribed period of delay. 
   
   
     3. The universal serial bus circuit according to  claim 1 , further comprising:
 a first selector pair for selecting execution or non-execution of timing matching by said first flip-flop pair, 
 a second selector pair for selecting execution or non-execution of timing matching by said second flip-flop pair, 
 a third selector pair for selecting execution or non-execution of timing matching by said third flip-flop pair, 
 a fourth selector pair for selecting execution or non-execution of timing matching by said fourth flip-flop pair.