Differential clock signals encoded with data

Abstract

The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock from pulsing. A clock-receiving chip detects the both-low or stopped differential clock and determines which control signal was asserted or de-asserted. A phase-locked loop (PLL) in the receiver keeps an internal clock running even when the differential clock is missing pulses. A sequence of M1 missing clock pulses, followed by N1 clock pulses, followed by M2 missing pulses encodes the control signal, where M1, N1, and M2 are whole numbers.

1. An interface between a clock-transmitting chip and a clock-receiving chip comprising:
 a plurality of control signals in the clock-transmitting chip, the plurality of control signals for controlling operation of the clock-receiving chip; 
 a plurality of received control signals in the clock-receiving chip, the plurality of received control signals for controlling operation of the clock-receiving chip; 
 a transmit clock in the clock-transmitting chip; 
 a differential driver in the clock-transmitting chip, receiving the transmit clock and driving a true differential clock line and a complement differential clock line with opposite states during normal operation when the transmit clock is sent from the clock-transmitting chip to the clock-receiving chip over the true and complement differential clock lines; 
 a differential receiver in the clock-receiving chip, the differential receiver receiving the true and complement differential clock lines and generating a receive clock; 
 an encoder in the clock-transmitting chip that receives the plurality of control signals, for outputting a pre-defined sequence on a blocking signal to the differential driver, the pre-defined sequence indicating a change in one of the plurality of control signals; 
 wherein the differential driver alters the true and complement differential lines in the pre-defined sequence to indicate a control signal; 
 a decoder, in the clock-receiving chip, for determining the pre-defined sequence when the true and complement differential lines have been altered, and for changing one of the received control signals in the clock-receiving chip that corresponds to the pre-defined sequence; and 
 a phase-locked loop (PLL) in the clock-receiving chip that has the receive clock as an input, and outputs an internal clock for use by the clock-receiving chip, 
 wherein when the true and complement differential clock lines are altered, causing the receive clock to miss a clock pulse, the PLL continues to pulse the internal clock without missing a clock pulse; 
 wherein the pre-defined sequence include a first number of altered clock pulses, followed by a second number of un-altered clock pulses, followed by a third number of altered clock pulses; 
 wherein the first, second, and third numbers are at least one; 
 whereby changes in the plurality of control signals in the clock-transmitting chip are sent over the true and complement differential clock lines encoded in a pre-defined sequence and whereby alterations to the true and complement differential clock lines are filtered out by the PLL. 
 
   
   
     2. The interface of  claim 1  wherein the pre-defined sequence is one of a plurality of pre-defined sequences each indicating a different change to the plurality of control signals. 
   
   
     3. The interface of  claim 2  wherein the first and third numbers are one, while the second number is greater than one;
 wherein the second number is different for each of the plurality of pre-defined sequences, whereby the change in the plurality of control signals is encoded by different second numbers of un-altered clock pulses between altered pulses. 
 
   
   
     4. The interface of  claim 3  further comprising:
 a detect logic gate, in the clock-receiving chip, that receives the true differential clock line and the complement differential clock line and outputs a detect signal to the decoder to indicate when the true and complement differential clock lines are in an altered state; 
 wherein the decoder also receives the internal clock from the PLL, the decoder counting a number of internal clock pulses when the detect signal is first activated to determine the first number, and counting a number of internal clock pulses when the detect signal is de-activated before the detect signal is again activated to determine the second number. 
 
   
   
     5. The interface of  claim 4  wherein the altered state is detected when both the true and complement differential clock lines are both in a low state. 
   
   
     6. The interface of  claim 4  wherein the altered state is detected when both the true and complement differential clock lines are both in a high state. 
   
   
     7. The interface of  claim 2  wherein the differential driver has a blocking logic gate that receives the transmit clock and the blocking signal from the encoder and outputs an intermediate clock to a differential state that generates the true and complement differential clock lines;
 wherein the blocking logic gate stops the intermediate clock from pulsing when the blocking signal is activated by the encoder, 
 whereby the true and complement differential clock lines stop pulsing when the blocking signal is activated to alter the true and complement differential clock lines. 
 
   
   
     8. The interface of  claim 7  wherein the decoder receives the receive clock from the differential receiver and receives the internal clock from the PLL;
 wherein the decoder counts missing pulses of the receive clock to determine the first number, and counts pulses of the receive clock between missing pulses to determine the second number. 
 
   
   
     9. The interface of  claim 7  wherein the clock-transmitting chip is a memory controller and the clock-receiving chip is a memory. 
   
   
     10. A method for transmitting control information over a pair of differential clock lines comprising:
 when no changes occur in control information in a clock-transmitting chip: 
 applying a pulsing transmit clock signal representing a transmit clock to a differential driver; 
 generating differential signals changing in opposite directions on the pair of differential clock lines driven by the differential driver to transmit a differential clock to a clock-receiving chip; 
 generating a receive clock in the clock-receiving chip from the differential clock on the pair of differential clock lines; 
 when a change occurs to the control information in the clock-transmitting chip; 
 encoding the change by selecting a selected sequence in a plurality of pre-defined sequences, the selected sequence identifying the change; 
 altering the differential clock using the selected sequence and transmitting the differential clock with an alteration to the clock-receiving chip; 
 generating the receive clock in the clock-receiving chip from the differential clock on the pair of differential clock lines, the receive clock having missing pulses when alterations occur; 
 recovering a free-running internal clock from the receive clock, the internal clock not having missing pulses when the receive clock has missing pulses; 
 detecting when the differential clock has been altered, and determining a recovered sequence of alterations of the differential clock; and 
 determining a change to received control information in the clock-receiving chip from the recovered sequence; 
 wherein altering the differential clock using the selected sequence comprises: 
 altering the differential clock for a period of M1 pulses of the transmit clock; 
 not altering the differential clock, allowing the differential clock to pulse for a period of N1 pulses of the transmit clock; 
 altering the differential clock for a period of M2 pulses of the transmit clock; 
 wherein M1, N1, and M2 are whole numbers; 
 wherein at least one of M1, N1 and M2 are different for each sequence in the plurality of pre-defined sequences, 
 whereby M1, N1, and M2 together identify the selected sequence and whereby changes to control information are transmitted from the clock-transmitting chip to the clock-receiving chip by encoding alterations to the differential clock. 
 
   
   
     11. The method of  claim 10  wherein altering the differential clock comprises at least one of:
 (1) driving both differential signals to a low state rather than to opposite states; 
 (2) driving both differential signals to a high state rather than to opposite states; 
 (3) not driving either of the differential signals when the pulsing transmit clock pulses but allowing the differential signals to remain in a previous state. 
 
   
   
     12. The method of  claim 10  wherein the control information indicates a command in a plurality of commands, or indicates states of a plurality of control signals.