Sense amplifying magnetic tunnel device

Abstract

A sense amplifying magnetic tunnel (SAMT) device is disclosed. In a particular embodiment, a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel is provided. In addition, a spin valve memory (SVM) cell is provided electrically coupled to the gate electrode. The electrical coupling between the SVM cell and the gate electrode serves to provide a control potential to the gate. In addition, the coupling provides a gain to a current passed through the SAMT device.

1. A sense amplifying magnetic tunnel (SAMT) device comprising:
 a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode, and a tunneling gate oxide proximate to the channel; and 
 a spin valve memory (SVM) cell electrically coupled to the gate electrode. 
 
   
   
     2. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SAMT device is operable such that a current flow through the SVM cell provides an injected current into the channel through the tunneling gate oxide. 
   
   
     3. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SAMT device is operable such that a current flow through the SVM cell develops a gate electrode control potential. 
   
   
     4. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SVM cell is coupled in series to the gate electrode. 
   
   
     5. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SVM cell is coupled between a sense potential and the gate electrode. 
   
   
     6. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SAMT device is operable such that the tunneling property of the tunneling gate oxide provides a gain in a sense current applied through the SVM cell. 
   
   
     7. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SAMT device is a sense amplifying data storage device. 
   
   
     8. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SAMT device is a sense amplifying magnetic field sensor device. 
   
   
     9. The sense amplifying magnetic tunnel device of  claim 1 , wherein the SVM cell is a tunnel junction cell. 
   
   
     10. A sense amplifying magnetic tunnel (SAMT) device comprising:
 a cross-point array of adjustable resistor devices, each resistor device paired with and electrically coupled to an isolator device, the electrical coupling serving to provide a gain to a current passed through the paired adjustable resistor and isolator; 
 wherein each of the isolator devices is a field effect transistor (FET), the FET having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel, the adjustable resistor devices being spin valve memory (SVM) cells, each SVM cell electrically coupled to the gate electrode. 
 
   
   
     11. The sense amplifying magnetic tunnel device of  claim 10 , wherein the SVM cell is coupled in series to the gate electrode. 
   
   
     12. The sense amplifying magnetic tunnel device of  claim 10 , wherein the SVM cell is coupled between a sense potential and the gate electrode. 
   
   
     13. The sense amplifying magnetic tunnel device of  claim 10 , wherein the SAMT device is operable such that a current flow through the SVM cell provides an injected current into the channel through the tunneling gate oxide. 
   
   
     14. The sense amplifying magnetic tunnel device of  claim 10 , wherein the SAMT device is operable such that a current flow through the SVM cell develops a gate electrode control potential. 
   
   
     15. The sense amplifying magnetic tunnel device of  claim 10 , wherein the SAMT device is a sense amplifying data storage device. 
   
   
     16. The sense amplifying magnetic tunnel device of  claim 10 , wherein the SAMT device is a sense amplifying magnetic field sensor device. 
   
   
     17. A sense amplifying magnetic tunnel (SAMT) device comprising:
 at least one field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel; and 
 at least one spin valve memory (SVM) cell electrically coupled to the gate electrode of an FET, the SVM cell having:
 a first ferromagnetic layer; 
 an intermediate layer in contact with the first layer; 
 a second ferromagnetic layer in contact with the intermediate layer opposite from the first ferromagnetic layer. 
 
 
   
   
     18. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SVM cell is coupled in series with the gate electrode. 
   
   
     19. The sense amplifying data storage device of  claim 17 , wherein the SVM cell is coupled between a sense potential and the gate electrode. 
   
   
     20. The sense amplifying magnetic tunnel device of  claim 17 , wherein the intermediate layer and the tunneling gate oxide are comprised of substantially the same material. 
   
   
     21. The sense amplifying magnetic tunnel device of  claim 17 , wherein the intermediate layer is a tunnel junction. 
   
   
     22. The sense amplifying magnetic tunnel device of  claim 21 , wherein the tunneling properties junction properties of the tunneling gate oxide are substantially similar to the tunnel junction properties of the intermediate layer. 
   
   
     23. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SAMT device is operable such that a sense current flowing through the SVM cell when a voltage is applied to the SVM cell develops a gate electrode control potential. 
   
   
     24. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SAMT device is operable such that a sense current flowing through the SVM cell when a voltage is applied to the SVM cell provides an injected current into the channel through the tunneling gate oxide. 
   
   
     25. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SAMT device is operable such that the tunneling property of the tunneling gate oxide provides a gain in a sense current applied through the SVM cell. 
   
   
     26. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SAMT device is a two terminal device. 
   
   
     27. The sense amplifying magnetic tunnel device of  claim 17 , further including:
 a first electrical conductor coupled to the SVM cell; 
 a second electrical conductor coupled to the source; and 
 a third electrical conductor coupled to the drain; 
 wherein the first and third electrical conductors are electrically coupled. 
 
   
   
     28. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SAMT device is a sense amplifying data storage device. 
   
   
     29. The sense amplifying magnetic tunnel device of  claim 17 , wherein the SAMT device is a sense amplifying magnetic field sensor device. 
   
   
     30. The sense amplifying magnetic tunnel device of  claim 17 , wherein the first and second ferromagnetic layers each have a magnetic orientation, the SVM cell having an alterable resistance based upon the first layer magnetic orientation being substantially parallel or anti-parallel to the magnetic orientation of the second layer. 
   
   
     31. A computer system comprising:
 a main board; 
 at least one central processing unit (CPU) coupled to the main board; and 
 at least one memory store joined to the CPU by the main board, the memory store including;
 a plurality of parallel electrically conductive rows; and 
 a plurality of parallel electrically conductive columns crossing the conductive rows, each thereby forming plurality of intersections; 
 a plurality of sense amplifying magnetic tunnel (SAMT) devices in electrical contact with and located at an intersection between a conductive row and a conductive column, each SAMT device including:
 a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel; and 
 a spin valve memory (SVM) cell electrically coupled to the gate electrode of the FET, the SVM cell having:
 a first ferromagnetic layer; 
 an intermediate junction layer in contact with the first layer; 
 a second ferromagnetic layer in contact with the intermediate layer opposite from the first ferromagnetic layer. 
 
 
 
 
   
   
     32. The computer system of  claim 31 , wherein the SAMT device is operable such that a sense current flowing through the SVM cell when a voltage is applied to the SVM cell develops a gate electrode control potential. 
   
   
     33. The computer system of  claim 31 , wherein the SAMT device is operable such that a sense current flowing through the SVM cell when a voltage is applied to the SVM cell provides an injected current into the channel through the tunneling gate oxide. 
   
   
     34. The computer system of  claim 31 , wherein the SAMT device is operable such that the tunneling property of the tunneling gate oxide provides a gain in a sense current applied through the SVM cell.