Sequential control circuit

Abstract

A control circuit for driving a plurality of electrical loads, one at a time, has a converter circuit for receiving a DMX compatible digital control signal and extracting a plurality of address bits therefrom. A decoder circuit receives the digital address bits and generates a plurality of enable signals, each corresponding to a particular load. One of the load enable signals is in an active state and each other enable signal is in an inactive state at any one time. A relay circuit for receives the enable signals, and in response passes an electrical drive signal to the electrical load corresponding to the enable signal that is in the active state. The relay circuit preferably includes a plurality of relay devices each coupled to one of the enable signals and a plurality of discharge circuits for rapidly discharging each electrical load when the enable signal corresponding to that load changes from the active state to the inactive state.

What is claimed is:  
     
       1. A control circuit for sequentially driving a plurality of electrical loads from a single power supply comprising: 
       a converter circuit for receiving a DMX compatible digital control signal and extracting a plurality of address bits therefrom;  
       a decoder circuit for receiving the digital address bits and in response generating a plurality of enable signals, each corresponding to a particular electrical load, a subset of the load enable signals being in an active state and each other enable signal being in an inactive state at any one time; and  
       a relay circuit for receiving the plurality of enable signals, and in response passing an electrical drive signal to each electrical load corresponding to the subset of enable signals that is in the active state, wherein the relay circuit comprises a plurality of discharge circuits for rapidly discharging each electrical load to snap-off a load when the enable signal corresponding to that load changes from the active state to the inactive state.  
     
     
       2. The control circuit of  claim 1  wherein the converter circuit extracts M address bits and the decoder circuit generates N enable signals, and wherein N≦2 M  where M and N are integers. 
     
     
       3. The control circuit of  claim 2  wherein N=2 M . 
     
     
       4. The control circuit of  claim 1  wherein the converter circuit extracts the plurality of address bits from data bytes for one or more DMX channels in the control signal. 
     
     
       5. The control circuit of  claim 1  wherein the converter circuit extracts one address bit from a data byte for each of a plurality of DMX channels in the control signal. 
     
     
       6. The control circuit of  claim 1  wherein the converter circuit extracts the plurality of address bits from a data byte for a single DMX channel in the control signal. 
     
     
       7. The control circuit of  claim 1  wherein the converter circuit comprises an address switch for specifying a DMX start channel. 
     
     
       8. The control circuit of  claim 1  wherein the relay circuit comprises a first plurality of relay devices each coupled to one of the enable signals as well as to the load corresponding thereto, wherein when said enable signal is in the active state the relay device couples the electrical drive signal to the corresponding electrical load. 
     
     
       9. The control circuit of  claim 8  wherein each of the first relay devices comprises a solid state relay device. 
     
     
       10. The control circuit of  claim 8  wherein each of the first relay devices comprises an electromechanical relay device. 
     
     
       11. The control circuit of  claim 10  wherein each electromechanical relay device is coupled to one of the enable signals through a transistor. 
     
     
       12. The control circuit of  claim 1  wherein each discharge circuit comprises a second relay device. 
     
     
       13. The control circuit of  claim 12  wherein each of the second relay devices comprises a solid state relay device. 
     
     
       14. The control circuit of  claim 1  wherein each discharge circuit establishes a low impedance shunt connection across the corresponding electrical load when the enable signal corresponding to that load changes from the active state to the inactive state. 
     
     
       15. The control circuit of  claim 1  wherein the electrical drive signal is an AC voltage signal. 
     
     
       16. The control circuit of  claim 1  wherein the electrical drive signal is an AC voltage signal having a variable rms voltage. 
     
     
       17. The control circuit of  claim 16  wherein the DMX compatible digital control signal further includes control information for varying the rms voltage. 
     
     
       18. The control circuit of  claim 1  wherein the electrical drive signal has a variable frequency. 
     
     
       19. The control circuit of  claim 18  wherein the DMX compatible digital control signal further includes control information for varying the frequency of the electrical drive signal. 
     
     
       20. The control circuit of  claim 1  wherein the electrical loads are electro luminescent loads. 
     
     
       21. The control circuit of  claim 1  wherein the relay circuit is implemented on a plurality of boards, each board corresponding to a group of electrical loads. 
     
     
       22. The control circuit of  claim 1  wherein the decoder circuit and the relay circuit are implemented on a plurality of boards, each board corresponding to a group of electrical loads. 
     
     
       23. The control circuit of  claim 1  wherein the subset of load enable signals in an active state at any one time consists of only one load enable signal. 
     
     
       24. A control circuit for sequentially driving a plurality of electro luminescent loads from a single power supply comprising: 
       a decoder circuit for receiving a digital address signal and in response generating a plurality of enable signals, each corresponding to a particular electrical load, a subset of the load enable signals being in an active state and each other enable signal being in an inactive state at any one time; and  
       a relay circuit comprising  
       a plurality of first relay devices each coupled to one of the plurality of enable signals as well as to the load corresponding thereto, wherein when said enable signal is in the active state the relay device couples the electrical drive signal to the corresponding electrical load, and  
       a plurality of discharge circuits for rapidly discharging each electrical load to snap-off a load when the enable signal corresponding to that load changes from the active state to the inactive state.  
     
     
       25. The control circuit of  claim 24  wherein each discharge circuit comprises a second relay device. 
     
     
       26. The control circuit of  claim 25  wherein each of the first and second relay devices comprises a solid state relay device. 
     
     
       27. The control circuit of  claim 24  wherein each discharge circuit establishes a low impedance shunt connection across the corresponding electrical load when the enable signal corresponding to that load changes from the active state to the inactive state.